169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) {  in getEEWAndEMUL()  argument
171   switch (Opcode) {  in getEEWAndEMUL()
208 bool opcodeHasEEWAndEMULInfo(unsigned short Opcode) {  in opcodeHasEEWAndEMULInfo()  argument
209   return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V ||  in opcodeHasEEWAndEMULInfo()
210          Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V ||  in opcodeHasEEWAndEMULInfo()
211          Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V ||  in opcodeHasEEWAndEMULInfo()
212          Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V ||  in opcodeHasEEWAndEMULInfo()
213          Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V ||  in opcodeHasEEWAndEMULInfo()
214          Opcode == RISCV::VLSE8_V || Opcode == RISCV::VSSE8_V ||  in opcodeHasEEWAndEMULInfo()
215          Opcode == RISCV::VLSE16_V || Opcode == RISCV::VSSE16_V ||  in opcodeHasEEWAndEMULInfo()
216          Opcode == RISCV::VLSE32_V || Opcode == RISCV::VSSE32_V ||  in opcodeHasEEWAndEMULInfo()
217          Opcode == RISCV::VLSE64_V || Opcode == RISCV::VSSE64_V;  in opcodeHasEEWAndEMULInfo()
223   unsigned short Opcode = MCI.getOpcode();  in getSchedClassID()  local
224   unsigned SchedClassID = MCII.get(Opcode).getSchedClass();  in getSchedClassID()
251   if (opcodeHasEEWAndEMULInfo(Opcode)) {  in getSchedClassID()
253     auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW);  in getSchedClassID()
254     RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW);  in getSchedClassID()
257     RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);  in getSchedClassID()
260       RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);  in getSchedClassID()
267                << MCII.getName(Opcode)  in getSchedClassID()
277                     << MCII.getName(Opcode) << ", LMUL=" << LI->getData()  in getSchedClassID()