| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 143 MachineInstr *DefInst = MO.getParent(); in checkADDrr() local
144 unsigned Opcode = DefInst->getOpcode(); in checkADDrr()
156 const MachineOperand &ImmOp = DefInst->getOperand(2); in checkADDrr()
164 const MachineOperand &Opnd = DefInst->getOperand(0); in checkADDrr()
169 BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp)) in checkADDrr()
170 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
172 DefInst->eraseFromParent(); in checkADDrr()
333 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg); in removeLD() local
334 if (!DefInst) in removeLD()
337 if (DefInst->getOpcode() != BPF::LD_imm64) in removeLD()
[all …]
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| /llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUMemoryUtils.cpp | |
| /llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 681 Instruction *DefInst = nullptr;
690 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), in LoadValue()
1245 if (InVal.DefInst == nullptr) in handleBranchCondition()
1260 Instruction *Matching = MemInstMatching ? MemInst.get() : InVal.DefInst; in getMatchingValue()
1261 Instruction *Other = MemInstMatching ? InVal.DefInst : MemInst.get(); in getMatchingValue()
1268 if (MemInst.isStore() && InVal.DefInst != Result) in getMatchingValue()
1277 if (!isNonTargetIntrinsicMatch(cast<IntrinsicInst>(InVal.DefInst), in getMatchingValue()
1283 !isSameMemGeneration(InVal.Generation, CurrentGeneration, InVal.DefInst, in getMatchingValue()
1594 << " to: " << *InVal.DefInst << '\n'); in processNode()
1705 if (InVal.DefInst in processNode()
680 Instruction *DefInst = nullptr; global() member
[all...] |
| H A D | DeadStoreElimination.cpp | 823 DefInst = MemDef->getMemoryInst();
829 Instruction *DefInst;
838 DefInst = MemDef->getMemoryInst();
843 Instruction *DefInst;
1246 /// (stored by \p DefInst). in isMemTerminator()
1247 bool isCompleteOverwrite(const MemoryLocation &DefLoc, Instruction *DefInst, in isMemTerminator()
1261 return isOverwrite(UseInst, DefInst, *CC, DefLoc, InstWriteOffset, in isMemTerminator()
2195 Instruction *DefInst = Def->getMemoryInst(); in eliminateDeadStores()
2196 auto MaybeDefLoc = getLocForWrite(DefInst); in eliminateDeadStores()
2197 if (!MaybeDefLoc || !isRemovable(DefInst)) in eliminateDeadStores()
2089 Instruction *DefInst = Def->getMemoryInst(); eliminateRedundantStoresOfExistingValues() local
[all...] |
| H A D | NewGVN.cpp | 4003 auto *DefInst = dyn_cast_or_null<Instruction>(Def); in eliminateInstructions()
4004 if (DefInst && AllTempInstructions.count(DefInst)) { in eliminateInstructions()
4005 auto *PN = cast<PHINode>(DefInst); in eliminateInstructions()
3965 auto *DefInst = dyn_cast_or_null<Instruction>(Def); eliminateInstructions() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 256 MachineBasicBlock::iterator DefInst; in addLinkerOpt()
318 MachineBasicBlock::iterator BBI = Pair->DefInst; in addLinkerOpt()
341 Pair->DefInst->addOperand(ImplDef); in addLinkerOpt()
349 Pair->DefInst->addOperand(*MF, PCRelLabel); in addLinkerOpt()
257 MachineBasicBlock::iterator DefInst; addLinkerOpt() member
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| H A D | PPCBranchCoalescing.cpp | 464 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg()); in canMoveToEnd() local
465 if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) { in canMoveToEnd()
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 407 MachineInstr *DefInst = LastDef[Reg]; in findPotentialNewifiableTFRs() local
408 if (!DefInst) in findPotentialNewifiableTFRs()
410 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs()
415 MachineBasicBlock::iterator It(DefInst); in findPotentialNewifiableTFRs()
426 PotentiallyNewifiableTFR.insert(DefInst); in findPotentialNewifiableTFRs()
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 507 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveOut()
508 if (DefInst.getParent() != MBB) { in mayLiveOut()
512 if (!SelfLoopDef || dominates(PosIndexes, DefInst, *SelfLoopDef)) in mayLiveOut()
513 SelfLoopDef = &DefInst; in mayLiveOut()
555 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveIn()
556 if (DefInst.getParent() != MBB || ++C >= Limit) { in mayLiveIn()
504 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { mayLiveOut() local
552 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { mayLiveIn() local
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| H A D | ModuloSchedule.cpp | 2319 MachineInstr *DefInst = MRI.getVRegDef(OrigReg); in updateInstrUse()
2320 if (!DefInst || DefInst->getParent() != OrigKernel) in updateInstrUse()
2324 if (DefInst->isPHI()) { in updateInstrUse()
2327 getPhiRegs(*DefInst, OrigKernel, InitReg, LoopReg); in updateInstrUse()
2330 DefInst = MRI.getVRegDef(LoopReg); in updateInstrUse()
2332 unsigned DefStageNum = Schedule.getStage(DefInst); in updateInstrUse()
2315 MachineInstr *DefInst = MRI.getVRegDef(OrigReg); updateInstrUse() local
|
| /llvm-project/llvm/lib/Analysis/ |
| H A D | MemorySSA.cpp | 284 Instruction *DefInst = MD->getMemoryInst(); in instructionClobbersQuery() local
285 assert(DefInst && "Defining instruction not actually an instruction"); in instructionClobbersQuery()
287 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) { in instructionClobbersQuery()
314 ModRefInfo I = AA.getModRefInfo(DefInst, CB); in instructionClobbersQuery()
318 if (auto *DefLoad = dyn_cast<LoadInst>(DefInst)) in instructionClobbersQuery()
322 ModRefInfo I = AA.getModRefInfo(DefInst, UseLoc); in instructionClobbersQuery()
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 554 const MachineInstr *DefInst = Def.getParent(); in foldToImm()
555 if (!TII->isFoldableCopy(*DefInst)) in foldToImm()
558 const MachineOperand &Copied = DefInst->getOperand(1); in foldToImm()
549 const MachineInstr *DefInst = Def.getParent(); foldToImm() local
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| H A D | SIInstrInfo.cpp | 9536 auto *DefInst = MRI.getVRegDef(RSR.Reg); in getInstrLatency()
9537 while (auto *MI = DefInst) { in getInstrLatency()
9538 DefInst = nullptr; in getInstrLatency()
9547 DefInst = MRI.getVRegDef(RSR.Reg); in getGenericInstructionUniformity()
9555 DefInst = MRI.getVRegDef(RSR.Reg); in getGenericInstructionUniformity()
9558 if (!DefInst) in getGenericInstructionUniformity()
9335 auto *DefInst = MRI.getVRegDef(RSR.Reg); getVRegSubRegDef() local
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| /llvm-project/polly/lib/Transform/ |
| H A D | DeLICM.cpp | 678 auto *DefInst = DefMA->getAccessInstruction(); in tryMapValue() local
721 LI->getLoopFor(DefInst->getParent())); in tryMapValue()
|