[PowerPC] Remove unused includes (NFC) (#116163)

Identified with misc-include-cleaner.

[Target] Use StringRef::operator== instead of StringRef::equals (NFC) (#91072) (#91138)

I'm planning to remove StringRef::equals in favor of
StringRef::operator==.

- StringRef::operator==/!= out

[Target] Use StringRef::operator== instead of StringRef::equals (NFC) (#91072) (#91138)

I'm planning to remove StringRef::equals in favor of
StringRef::operator==.

- StringRef::operator==/!= outnumber StringRef::equals by a factor of
38 under llvm/ in terms of their usage.

- The elimination of StringRef::equals brings StringRef closer to
std::string_view, which has operator== but not equals.

- S == "foo" is more readable than S.equals("foo"), especially for
!Long.Expression.equals("str") vs Long.Expression != "str".

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[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many

[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.

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[PowerPC] redesign the target flags (#69695)

12 bit is not enough for PPC's target specific flags. If 8 bit for the
bitmask flags, 4 bit for the direct mask, PPC can total have 16 direct
mask and

[PowerPC] redesign the target flags (#69695)

12 bit is not enough for PPC's target specific flags. If 8 bit for the
bitmask flags, 4 bit for the direct mask, PPC can total have 16 direct
mask and 8 bitmask. Not enough for PPC, see this issue in
https://github.com/llvm/llvm-project/pull/66316

Redesign how PPC target set the target specific flags. With this patch,
all ppc target flags are direct flags. No bitmask flag in PPC anymore.

This patch aligns with some targets like X86 which also has many target
specific flags.

The patch also fixes a bug related to flag `MO_TLSGDM_FLAG` and `MO_LO`.
They are the same value and the test case changes in this PR shows the
bug.

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[llvm] Stop including llvm/ADT/DenseMap.h (NFC)

Ientified with clangd.

[PowerPC] Improve kill flag computation and add verification after MI peephole

The MI Peephole pass has grown to include a large number of transformations over the years. Many of the transformations

[PowerPC] Improve kill flag computation and add verification after MI peephole

The MI Peephole pass has grown to include a large number of transformations over the years. Many of the transformations require re-computation of kill flags but don't do a good job of re-computing them. This causes us to have very common failures when the compiler is built with expensive checks. Over time, we added and augmented a function that is supposed to go and fix up kill flags after each transformation but we keep missing cases.
This patch does the following:
- Removes the function to re-compute kill flags
- Adds LiveVariables to compute and maintain kill flags while transforming code
- Adds re-computation of kill flags for the post-RA peepholes for each block that contains a transformed instruction

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D133103

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[PowerPC] Optimize compare by using record form in post-RA.

Summary: We currently optimize the comparison only in SSA, therefore we will miss some optimization opportunities where the input of compa

[PowerPC] Optimize compare by using record form in post-RA.

Summary: We currently optimize the comparison only in SSA, therefore we will miss some optimization opportunities where the input of comparison is lowered from COPY in post-RA.
Ie. ExpandPostRA::LowerCopy is called after PPCInstrInfo::optimizeCompareInstr.
This patch optimizes the comparison in post-RA and only the cases that compare against zero can be handled.
D131374 converts the comparison and its user to a compare against zero with the appropriate predicate on the branch, which creates additional opportunities for this patch.

Reviewed By: shchenz, lkail

Differential Revision: https://reviews.llvm.org/D131873

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[llvm] Fix comment typos (NFC)

[PowerPC] Set the special DSCR with a compiler option.

Add a compiler option and the instructions required to set the
special Data Stream Control Register (DSCR). The special register will
not be se

[PowerPC] Set the special DSCR with a compiler option.

Add a compiler option and the instructions required to set the
special Data Stream Control Register (DSCR). The special register will
not be set by default.

Original patch by: Muhammad Usman

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D117013

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[MC] Split MCContext::createTempSymbol, default AlwaysAddSuffix to true, and add comments

CanBeUnnamed is rarely false. Splitting to a createNamedTempSymbol makes the
intention clearer and matches t

[MC] Split MCContext::createTempSymbol, default AlwaysAddSuffix to true, and add comments

CanBeUnnamed is rarely false. Splitting to a createNamedTempSymbol makes the
intention clearer and matches the direction of reverted r240130 (to drop the
unneeded parameters).

No behavior change.

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Migrate MCContext::createTempSymbol call sites to AlwaysAddSuffix=true

Most call sites set AlwaysAddSuffix to true. The two use cases do not really
need false and can be more consistent with other t

Migrate MCContext::createTempSymbol call sites to AlwaysAddSuffix=true

Most call sites set AlwaysAddSuffix to true. The two use cases do not really
need false and can be more consistent with other temporary symbol usage.

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[Target, Transforms] Use contains (NFC)

Revert "[PowerPC] Extend folding RLWINM + RLWINM to post-RA."

This reverts commit 1c0941e1524f499e3fbde48fc3bdd0e70fc8f2e4.

[PowerPC] Extend folding RLWINM + RLWINM to post-RA.

Summary: We have the patterns to fold 2 RLWINMs before RA, while some RLWINM will be generated after RA, for example rGc4690b007743. If the RLWIN

[PowerPC] Extend folding RLWINM + RLWINM to post-RA.

Summary: We have the patterns to fold 2 RLWINMs before RA, while some RLWINM will be generated after RA, for example rGc4690b007743. If the RLWINM generated after RA followed by another RLWINM, we expect to perform the optimization too.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D89855

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[PowerPC] Add peephole to remove redundant accumulator prime/unprime instructions

In some situations, the compiler may insert an accumulator prime instruction and
an accumulator unprime instruction

[PowerPC] Add peephole to remove redundant accumulator prime/unprime instructions

In some situations, the compiler may insert an accumulator prime instruction and
an accumulator unprime instruction with no use of that accumulator between the two.
That's for example the case when we store an accumulator after assembling it or
restoring it. This patch adds a peephole to remove these prime and unprime instructions.

Differential Revision: https://reviews.llvm.org/D91386

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Revert "[PowerPC] Extend folding RLWINM + RLWINM to post-RA."

This reverts commit 119ab2181e6ed823849c93d55af8e989c28c9f3c.

[PowerPC] Extend folding RLWINM + RLWINM to post-RA.

Summary: This patch depends on D89846. We have the patterns to fold 2 RLWINMs in ppc-mi-peephole, while some RLWINM will be generated after RA, f

[PowerPC] Extend folding RLWINM + RLWINM to post-RA.

Summary: This patch depends on D89846. We have the patterns to fold 2 RLWINMs in ppc-mi-peephole, while some RLWINM will be generated after RA, for example rGc4690b007743. If the RLWINM generated after RA followed by another RLWINM, we expect to perform the optimization after RA, too.

Reviewed By: shchenz, steven.zhang

Differential Revision: https://reviews.llvm.org/D89855

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[PowerPC] Add option to control PCRel GOT indirect linker optimization

Add a hidden option to the compiler to control a the PC Relative GOT indirect
linker optimization.

If this option is set to fa

[PowerPC] Add option to control PCRel GOT indirect linker optimization

Add a hidden option to the compiler to control a the PC Relative GOT indirect
linker optimization.

If this option is set to false the compiler will no loger produce the
relocations required by the linker to perform the optimization.

Reviewed By: nemanjai, NeHuang, #powerpc

Differential Revision: https://reviews.llvm.org/D85377

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[PowerPC] Add linker opt for PC Relative GOT indirect accesses

A linker optimization is available on PowerPC for GOT indirect PCRelative loads.

The idea is that we can mark a usual GOT indirect loa

[PowerPC] Add linker opt for PC Relative GOT indirect accesses

A linker optimization is available on PowerPC for GOT indirect PCRelative loads.

The idea is that we can mark a usual GOT indirect load:

pld 3, vec@got@pcrel(0), 1
lwa 3, 4(3)

With a relocation to say that if we don't need to go through the GOT we can let
the linker further optimize this and replace a load with a nop.

pld 3, vec@got@pcrel(0), 1
.Lpcrel1:
.reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
lwa 3, 4(3)

This patch adds the logic that allows the compiler to add the R_PPC64_PCREL_OPT.

Reviewers: nemanjai, lei, hfinkel, sfertile, efriedma, tstellar, grosbach

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D79864

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[PowerPC] Bail out of redundant LI elimination on an implicit kill

The transformation currently does not differentiate between explicit
and implicit kills. However, it is not valid to later simply c

[PowerPC] Bail out of redundant LI elimination on an implicit kill

The transformation currently does not differentiate between explicit
and implicit kills. However, it is not valid to later simply clear
an implicit kill flag since the kill could be due to a call or return.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=45374

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[PowerPC] Remove redundant CRSET/CRUNSET in custom lowering of known CR bit spills

We lower known CR bit spills (CRSET/CRUNSET) to load and spill the known value
but forgot to remove the redundant s

[PowerPC] Remove redundant CRSET/CRUNSET in custom lowering of known CR bit spills

We lower known CR bit spills (CRSET/CRUNSET) to load and spill the known value
but forgot to remove the redundant spills.

e.g., This sequence was used to spill a CRUNSET:
crclr 4*cr5+lt
mfocrf r3,4
rlwinm r3,r3,20,0,0
stw r3,132(r1)

Custom lowering of known CR bit spills lower it to:
crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt
li r3,0
stw r3,132(r1)

crxor is redundant if there is no use of 4*cr5+lt so we should remove it

Differential revision: https://reviews.llvm.org/D67722

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[PowerPC] [Peephole] fold frame offset by using index form to save add.

renamable $x6 = ADDI8 $x1, -80 ;;; 0 is replaced with -80
renamable $x6 = ADD8 killed renamable $x6, renamable $x5
STW ki

[PowerPC] [Peephole] fold frame offset by using index form to save add.

renamable $x6 = ADDI8 $x1, -80 ;;; 0 is replaced with -80
renamable $x6 = ADD8 killed renamable $x6, renamable $x5
STW killed renamable $r3, 4, killed renamable $x6 :: (store 4 into %ir.14, !tbaa !2)

After PEI there is a peephole opt opportunity to combine above -80 in ADDI8 with 4 in the STW to eliminate unnecessary ADD8.

Expected result:
renamable $x6 = ADDI8 $x1, -76
STWX killed renamable $r3, renamable $x5, killed renamable $x6 :: (store 4 into %ir.6, !tbaa !2)

Reviewed by: stefanp

Differential Revision: https://reviews.llvm.org/D66329

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[PowerPC] Remove assertion "Shouldn't overwrite a register before it is killed"

The assertion is everzealous and fail tests like:

renamable $x3 = LI8 0
STD renamable $x3, 16, $x1
renamable $x

[PowerPC] Remove assertion "Shouldn't overwrite a register before it is killed"

The assertion is everzealous and fail tests like:

renamable $x3 = LI8 0
STD renamable $x3, 16, $x1
renamable $x3 = LI8 0

Remove the assertion since killed flag of $x3 is not mandentory.

Differential Revision: https://reviews.llvm.org/D68344

llvm-svn: 374515

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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM

Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Re

Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM

Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).

Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor

Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&

Depends on D65919

Reviewers: arsenm, bogner, craig.topper, RKSimon

Reviewed By: arsenm

Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65962

llvm-svn: 369041

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[PowerPC] Remove redundant load immediate instructions

Currently PowerPC backend emits code like this:

r3 = li 0
std r3, 264(r1)
r3 = li 0
std r3, 272(r1)

This patch fixes that and other c

[PowerPC] Remove redundant load immediate instructions

Currently PowerPC backend emits code like this:

r3 = li 0
std r3, 264(r1)
r3 = li 0
std r3, 272(r1)

This patch fixes that and other cases where a register already contains a value that is loaded so we will get:

r3 = li 0
std r3, 264(r1)
std r3, 272(r1)

Differential Revision: https://reviews.llvm.org/D64220

llvm-svn: 366840

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