1 //===--------- PPCPreEmitPeephole.cpp - Late peephole optimizations -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // A pre-emit peephole for catching opportunities introduced by late passes such 10 // as MachineBlockPlacement. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPC.h" 15 #include "PPCInstrInfo.h" 16 #include "PPCSubtarget.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/Statistic.h" 19 #include "llvm/CodeGen/LivePhysRegs.h" 20 #include "llvm/CodeGen/MachineBasicBlock.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/MC/MCContext.h" 25 #include "llvm/Support/CommandLine.h" 26 #include "llvm/Support/Debug.h" 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "ppc-pre-emit-peephole" 31 32 STATISTIC(NumRRConvertedInPreEmit, 33 "Number of r+r instructions converted to r+i in pre-emit peephole"); 34 STATISTIC(NumRemovedInPreEmit, 35 "Number of instructions deleted in pre-emit peephole"); 36 STATISTIC(NumberOfSelfCopies, 37 "Number of self copy instructions eliminated"); 38 STATISTIC(NumFrameOffFoldInPreEmit, 39 "Number of folding frame offset by using r+r in pre-emit peephole"); 40 STATISTIC(NumRotateInstrFoldInPreEmit, 41 "Number of folding Rotate instructions in pre-emit peephole"); 42 43 static cl::opt<bool> 44 EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true), 45 cl::desc("enable PC Relative linker optimization")); 46 47 static cl::opt<bool> 48 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true), 49 cl::desc("Run pre-emit peephole optimizations.")); 50 51 namespace { 52 53 static bool hasPCRelativeForm(MachineInstr &Use) { 54 switch (Use.getOpcode()) { 55 default: 56 return false; 57 case PPC::LBZ: 58 case PPC::LBZ8: 59 case PPC::LHA: 60 case PPC::LHA8: 61 case PPC::LHZ: 62 case PPC::LHZ8: 63 case PPC::LWZ: 64 case PPC::LWZ8: 65 case PPC::STB: 66 case PPC::STB8: 67 case PPC::STH: 68 case PPC::STH8: 69 case PPC::STW: 70 case PPC::STW8: 71 case PPC::LD: 72 case PPC::STD: 73 case PPC::LWA: 74 case PPC::LXSD: 75 case PPC::LXSSP: 76 case PPC::LXV: 77 case PPC::STXSD: 78 case PPC::STXSSP: 79 case PPC::STXV: 80 case PPC::LFD: 81 case PPC::LFS: 82 case PPC::STFD: 83 case PPC::STFS: 84 case PPC::DFLOADf32: 85 case PPC::DFLOADf64: 86 case PPC::DFSTOREf32: 87 case PPC::DFSTOREf64: 88 return true; 89 } 90 } 91 92 class PPCPreEmitPeephole : public MachineFunctionPass { 93 public: 94 static char ID; 95 PPCPreEmitPeephole() : MachineFunctionPass(ID) { 96 initializePPCPreEmitPeepholePass(*PassRegistry::getPassRegistry()); 97 } 98 99 void getAnalysisUsage(AnalysisUsage &AU) const override { 100 MachineFunctionPass::getAnalysisUsage(AU); 101 } 102 103 MachineFunctionProperties getRequiredProperties() const override { 104 return MachineFunctionProperties().set( 105 MachineFunctionProperties::Property::NoVRegs); 106 } 107 108 // This function removes any redundant load immediates. It has two level 109 // loops - The outer loop finds the load immediates BBI that could be used 110 // to replace following redundancy. The inner loop scans instructions that 111 // after BBI to find redundancy and update kill/dead flags accordingly. If 112 // AfterBBI is the same as BBI, it is redundant, otherwise any instructions 113 // that modify the def register of BBI would break the scanning. 114 // DeadOrKillToUnset is a pointer to the previous operand that had the 115 // kill/dead flag set. It keeps track of the def register of BBI, the use 116 // registers of AfterBBIs and the def registers of AfterBBIs. 117 bool removeRedundantLIs(MachineBasicBlock &MBB, 118 const TargetRegisterInfo *TRI) { 119 LLVM_DEBUG(dbgs() << "Remove redundant load immediates from MBB:\n"; 120 MBB.dump(); dbgs() << "\n"); 121 122 DenseSet<MachineInstr *> InstrsToErase; 123 for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) { 124 // Skip load immediate that is marked to be erased later because it 125 // cannot be used to replace any other instructions. 126 if (InstrsToErase.find(&*BBI) != InstrsToErase.end()) 127 continue; 128 // Skip non-load immediate. 129 unsigned Opc = BBI->getOpcode(); 130 if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS && 131 Opc != PPC::LIS8) 132 continue; 133 // Skip load immediate, where the operand is a relocation (e.g., $r3 = 134 // LI target-flags(ppc-lo) %const.0). 135 if (!BBI->getOperand(1).isImm()) 136 continue; 137 assert(BBI->getOperand(0).isReg() && 138 "Expected a register for the first operand"); 139 140 LLVM_DEBUG(dbgs() << "Scanning after load immediate: "; BBI->dump();); 141 142 Register Reg = BBI->getOperand(0).getReg(); 143 int64_t Imm = BBI->getOperand(1).getImm(); 144 MachineOperand *DeadOrKillToUnset = nullptr; 145 if (BBI->getOperand(0).isDead()) { 146 DeadOrKillToUnset = &BBI->getOperand(0); 147 LLVM_DEBUG(dbgs() << " Kill flag of " << *DeadOrKillToUnset 148 << " from load immediate " << *BBI 149 << " is a unsetting candidate\n"); 150 } 151 // This loop scans instructions after BBI to see if there is any 152 // redundant load immediate. 153 for (auto AfterBBI = std::next(BBI); AfterBBI != MBB.instr_end(); 154 ++AfterBBI) { 155 // Track the operand that kill Reg. We would unset the kill flag of 156 // the operand if there is a following redundant load immediate. 157 int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI); 158 159 // We can't just clear implicit kills, so if we encounter one, stop 160 // looking further. 161 if (KillIdx != -1 && AfterBBI->getOperand(KillIdx).isImplicit()) { 162 LLVM_DEBUG(dbgs() 163 << "Encountered an implicit kill, cannot proceed: "); 164 LLVM_DEBUG(AfterBBI->dump()); 165 break; 166 } 167 168 if (KillIdx != -1) { 169 assert(!DeadOrKillToUnset && "Shouldn't kill same register twice"); 170 DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx); 171 LLVM_DEBUG(dbgs() 172 << " Kill flag of " << *DeadOrKillToUnset << " from " 173 << *AfterBBI << " is a unsetting candidate\n"); 174 } 175 176 if (!AfterBBI->modifiesRegister(Reg, TRI)) 177 continue; 178 // Finish scanning because Reg is overwritten by a non-load 179 // instruction. 180 if (AfterBBI->getOpcode() != Opc) 181 break; 182 assert(AfterBBI->getOperand(0).isReg() && 183 "Expected a register for the first operand"); 184 // Finish scanning because Reg is overwritten by a relocation or a 185 // different value. 186 if (!AfterBBI->getOperand(1).isImm() || 187 AfterBBI->getOperand(1).getImm() != Imm) 188 break; 189 190 // It loads same immediate value to the same Reg, which is redundant. 191 // We would unset kill flag in previous Reg usage to extend live range 192 // of Reg first, then remove the redundancy. 193 if (DeadOrKillToUnset) { 194 LLVM_DEBUG(dbgs() 195 << " Unset dead/kill flag of " << *DeadOrKillToUnset 196 << " from " << *DeadOrKillToUnset->getParent()); 197 if (DeadOrKillToUnset->isDef()) 198 DeadOrKillToUnset->setIsDead(false); 199 else 200 DeadOrKillToUnset->setIsKill(false); 201 } 202 DeadOrKillToUnset = 203 AfterBBI->findRegisterDefOperand(Reg, true, true, TRI); 204 if (DeadOrKillToUnset) 205 LLVM_DEBUG(dbgs() 206 << " Dead flag of " << *DeadOrKillToUnset << " from " 207 << *AfterBBI << " is a unsetting candidate\n"); 208 InstrsToErase.insert(&*AfterBBI); 209 LLVM_DEBUG(dbgs() << " Remove redundant load immediate: "; 210 AfterBBI->dump()); 211 } 212 } 213 214 for (MachineInstr *MI : InstrsToErase) { 215 MI->eraseFromParent(); 216 } 217 NumRemovedInPreEmit += InstrsToErase.size(); 218 return !InstrsToErase.empty(); 219 } 220 221 // Check if this instruction is a PLDpc that is part of a GOT indirect 222 // access. 223 bool isGOTPLDpc(MachineInstr &Instr) { 224 if (Instr.getOpcode() != PPC::PLDpc) 225 return false; 226 227 // The result must be a register. 228 const MachineOperand &LoadedAddressReg = Instr.getOperand(0); 229 if (!LoadedAddressReg.isReg()) 230 return false; 231 232 // Make sure that this is a global symbol. 233 const MachineOperand &SymbolOp = Instr.getOperand(1); 234 if (!SymbolOp.isGlobal()) 235 return false; 236 237 // Finally return true only if the GOT flag is present. 238 return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG); 239 } 240 241 bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) { 242 MachineFunction *MF = MBB.getParent(); 243 // If the linker opt is disabled then just return. 244 if (!EnablePCRelLinkerOpt) 245 return false; 246 247 // Add this linker opt only if we are using PC Relative memops. 248 if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls()) 249 return false; 250 251 // Struct to keep track of one def/use pair for a GOT indirect access. 252 struct GOTDefUsePair { 253 MachineBasicBlock::iterator DefInst; 254 MachineBasicBlock::iterator UseInst; 255 Register DefReg; 256 Register UseReg; 257 bool StillValid; 258 }; 259 // Vector of def/ues pairs in this basic block. 260 SmallVector<GOTDefUsePair, 4> CandPairs; 261 SmallVector<GOTDefUsePair, 4> ValidPairs; 262 bool MadeChange = false; 263 264 // Run through all of the instructions in the basic block and try to 265 // collect potential pairs of GOT indirect access instructions. 266 for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) { 267 // Look for the initial GOT indirect load. 268 if (isGOTPLDpc(*BBI)) { 269 GOTDefUsePair CurrentPair{BBI, MachineBasicBlock::iterator(), 270 BBI->getOperand(0).getReg(), 271 PPC::NoRegister, true}; 272 CandPairs.push_back(CurrentPair); 273 continue; 274 } 275 276 // We haven't encountered any new PLD instructions, nothing to check. 277 if (CandPairs.empty()) 278 continue; 279 280 // Run through the candidate pairs and see if any of the registers 281 // defined in the PLD instructions are used by this instruction. 282 // Note: the size of CandPairs can change in the loop. 283 for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) { 284 GOTDefUsePair &Pair = CandPairs[Idx]; 285 // The instruction does not use or modify this PLD's def reg, 286 // ignore it. 287 if (!BBI->readsRegister(Pair.DefReg, TRI) && 288 !BBI->modifiesRegister(Pair.DefReg, TRI)) 289 continue; 290 291 // The use needs to be used in the address compuation and not 292 // as the register being stored for a store. 293 const MachineOperand *UseOp = 294 hasPCRelativeForm(*BBI) ? &BBI->getOperand(2) : nullptr; 295 296 // Check for a valid use. 297 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && 298 UseOp->isUse() && UseOp->isKill()) { 299 Pair.UseInst = BBI; 300 Pair.UseReg = BBI->getOperand(0).getReg(); 301 ValidPairs.push_back(Pair); 302 } 303 CandPairs.erase(CandPairs.begin() + Idx); 304 } 305 } 306 307 // Go through all of the pairs and check for any more valid uses. 308 for (auto Pair = ValidPairs.begin(); Pair != ValidPairs.end(); Pair++) { 309 // We shouldn't be here if we don't have a valid pair. 310 assert(Pair->UseInst.isValid() && Pair->StillValid && 311 "Kept an invalid def/use pair for GOT PCRel opt"); 312 // We have found a potential pair. Search through the instructions 313 // between the def and the use to see if it is valid to mark this as a 314 // linker opt. 315 MachineBasicBlock::iterator BBI = Pair->DefInst; 316 ++BBI; 317 for (; BBI != Pair->UseInst; ++BBI) { 318 if (BBI->readsRegister(Pair->UseReg, TRI) || 319 BBI->modifiesRegister(Pair->UseReg, TRI)) { 320 Pair->StillValid = false; 321 break; 322 } 323 } 324 325 if (!Pair->StillValid) 326 continue; 327 328 // The load/store instruction that uses the address from the PLD will 329 // either use a register (for a store) or define a register (for the 330 // load). That register will be added as an implicit def to the PLD 331 // and as an implicit use on the second memory op. This is a precaution 332 // to prevent future passes from using that register between the two 333 // instructions. 334 MachineOperand ImplDef = 335 MachineOperand::CreateReg(Pair->UseReg, true, true); 336 MachineOperand ImplUse = 337 MachineOperand::CreateReg(Pair->UseReg, false, true); 338 Pair->DefInst->addOperand(ImplDef); 339 Pair->UseInst->addOperand(ImplUse); 340 341 // Create the symbol. 342 MCContext &Context = MF->getContext(); 343 MCSymbol *Symbol = 344 Context.createTempSymbol(Twine("pcrel"), false, false); 345 MachineOperand PCRelLabel = 346 MachineOperand::CreateMCSymbol(Symbol, PPCII::MO_PCREL_OPT_FLAG); 347 Pair->DefInst->addOperand(*MF, PCRelLabel); 348 Pair->UseInst->addOperand(*MF, PCRelLabel); 349 MadeChange |= true; 350 } 351 return MadeChange; 352 } 353 354 // This function removes redundant pairs of accumulator prime/unprime 355 // instructions. In some situations, it's possible the compiler inserts an 356 // accumulator prime instruction followed by an unprime instruction (e.g. 357 // when we store an accumulator after restoring it from a spill). If the 358 // accumulator is not used between the two, they can be removed. This 359 // function removes these redundant pairs from basic blocks. 360 // The algorithm is quite straightforward - every time we encounter a prime 361 // instruction, the primed register is added to a candidate set. Any use 362 // other than a prime removes the candidate from the set and any de-prime 363 // of a current candidate marks both the prime and de-prime for removal. 364 // This way we ensure we only remove prime/de-prime *pairs* with no 365 // intervening uses. 366 bool removeAccPrimeUnprime(MachineBasicBlock &MBB) { 367 DenseSet<MachineInstr *> InstrsToErase; 368 // Initially, none of the acc registers are candidates. 369 SmallVector<MachineInstr *, 8> Candidates( 370 PPC::UACCRCRegClass.getNumRegs(), nullptr); 371 372 for (MachineInstr &BBI : MBB.instrs()) { 373 unsigned Opc = BBI.getOpcode(); 374 // If we are visiting a xxmtacc instruction, we add it and its operand 375 // register to the candidate set. 376 if (Opc == PPC::XXMTACC) { 377 Register Acc = BBI.getOperand(0).getReg(); 378 assert(PPC::ACCRCRegClass.contains(Acc) && 379 "Unexpected register for XXMTACC"); 380 Candidates[Acc - PPC::ACC0] = &BBI; 381 } 382 // If we are visiting a xxmfacc instruction and its operand register is 383 // in the candidate set, we mark the two instructions for removal. 384 else if (Opc == PPC::XXMFACC) { 385 Register Acc = BBI.getOperand(0).getReg(); 386 assert(PPC::ACCRCRegClass.contains(Acc) && 387 "Unexpected register for XXMFACC"); 388 if (!Candidates[Acc - PPC::ACC0]) 389 continue; 390 InstrsToErase.insert(&BBI); 391 InstrsToErase.insert(Candidates[Acc - PPC::ACC0]); 392 } 393 // If we are visiting an instruction using an accumulator register 394 // as operand, we remove it from the candidate set. 395 else { 396 for (MachineOperand &Operand : BBI.operands()) { 397 if (!Operand.isReg()) 398 continue; 399 Register Reg = Operand.getReg(); 400 if (PPC::ACCRCRegClass.contains(Reg)) 401 Candidates[Reg - PPC::ACC0] = nullptr; 402 } 403 } 404 } 405 406 for (MachineInstr *MI : InstrsToErase) 407 MI->eraseFromParent(); 408 NumRemovedInPreEmit += InstrsToErase.size(); 409 return !InstrsToErase.empty(); 410 } 411 412 bool runOnMachineFunction(MachineFunction &MF) override { 413 if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) { 414 // Remove UNENCODED_NOP even when this pass is disabled. 415 // This needs to be done unconditionally so we don't emit zeros 416 // in the instruction stream. 417 SmallVector<MachineInstr *, 4> InstrsToErase; 418 for (MachineBasicBlock &MBB : MF) 419 for (MachineInstr &MI : MBB) 420 if (MI.getOpcode() == PPC::UNENCODED_NOP) 421 InstrsToErase.push_back(&MI); 422 for (MachineInstr *MI : InstrsToErase) 423 MI->eraseFromParent(); 424 return false; 425 } 426 bool Changed = false; 427 const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 428 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 429 SmallVector<MachineInstr *, 4> InstrsToErase; 430 for (MachineBasicBlock &MBB : MF) { 431 Changed |= removeRedundantLIs(MBB, TRI); 432 Changed |= addLinkerOpt(MBB, TRI); 433 Changed |= removeAccPrimeUnprime(MBB); 434 for (MachineInstr &MI : MBB) { 435 unsigned Opc = MI.getOpcode(); 436 if (Opc == PPC::UNENCODED_NOP) { 437 InstrsToErase.push_back(&MI); 438 continue; 439 } 440 // Detect self copies - these can result from running AADB. 441 if (PPCInstrInfo::isSameClassPhysRegCopy(Opc)) { 442 const MCInstrDesc &MCID = TII->get(Opc); 443 if (MCID.getNumOperands() == 3 && 444 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() && 445 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) { 446 NumberOfSelfCopies++; 447 LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: "); 448 LLVM_DEBUG(MI.dump()); 449 InstrsToErase.push_back(&MI); 450 continue; 451 } 452 else if (MCID.getNumOperands() == 2 && 453 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) { 454 NumberOfSelfCopies++; 455 LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: "); 456 LLVM_DEBUG(MI.dump()); 457 InstrsToErase.push_back(&MI); 458 continue; 459 } 460 } 461 MachineInstr *DefMIToErase = nullptr; 462 if (TII->convertToImmediateForm(MI, &DefMIToErase)) { 463 Changed = true; 464 NumRRConvertedInPreEmit++; 465 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 466 LLVM_DEBUG(MI.dump()); 467 if (DefMIToErase) { 468 InstrsToErase.push_back(DefMIToErase); 469 } 470 } 471 if (TII->foldFrameOffset(MI)) { 472 Changed = true; 473 NumFrameOffFoldInPreEmit++; 474 LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: "); 475 LLVM_DEBUG(MI.dump()); 476 } 477 MachineInstr *ToErase = nullptr; 478 if (TII->simplifyRotateAndMaskInstr(MI, ToErase)) { 479 Changed = true; 480 NumRotateInstrFoldInPreEmit++; 481 if (ToErase) 482 InstrsToErase.push_back(ToErase); 483 } 484 } 485 486 // Eliminate conditional branch based on a constant CR bit by 487 // CRSET or CRUNSET. We eliminate the conditional branch or 488 // convert it into an unconditional branch. Also, if the CR bit 489 // is not used by other instructions, we eliminate CRSET as well. 490 auto I = MBB.getFirstInstrTerminator(); 491 if (I == MBB.instr_end()) 492 continue; 493 MachineInstr *Br = &*I; 494 if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn) 495 continue; 496 MachineInstr *CRSetMI = nullptr; 497 Register CRBit = Br->getOperand(0).getReg(); 498 unsigned CRReg = getCRFromCRBit(CRBit); 499 bool SeenUse = false; 500 MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend(); 501 for (It++; It != Er; It++) { 502 if (It->modifiesRegister(CRBit, TRI)) { 503 if ((It->getOpcode() == PPC::CRUNSET || 504 It->getOpcode() == PPC::CRSET) && 505 It->getOperand(0).getReg() == CRBit) 506 CRSetMI = &*It; 507 break; 508 } 509 if (It->readsRegister(CRBit, TRI)) 510 SeenUse = true; 511 } 512 if (!CRSetMI) continue; 513 514 unsigned CRSetOp = CRSetMI->getOpcode(); 515 if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) || 516 (Br->getOpcode() == PPC::BC && CRSetOp == PPC::CRUNSET)) { 517 // Remove this branch since it cannot be taken. 518 InstrsToErase.push_back(Br); 519 MBB.removeSuccessor(Br->getOperand(1).getMBB()); 520 } 521 else { 522 // This conditional branch is always taken. So, remove all branches 523 // and insert an unconditional branch to the destination of this. 524 MachineBasicBlock::iterator It = Br, Er = MBB.end(); 525 for (; It != Er; It++) { 526 if (It->isDebugInstr()) continue; 527 assert(It->isTerminator() && "Non-terminator after a terminator"); 528 InstrsToErase.push_back(&*It); 529 } 530 if (!MBB.isLayoutSuccessor(Br->getOperand(1).getMBB())) { 531 ArrayRef<MachineOperand> NoCond; 532 TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr, 533 NoCond, Br->getDebugLoc()); 534 } 535 for (auto &Succ : MBB.successors()) 536 if (Succ != Br->getOperand(1).getMBB()) { 537 MBB.removeSuccessor(Succ); 538 break; 539 } 540 } 541 542 // If the CRBit is not used by another instruction, we can eliminate 543 // CRSET/CRUNSET instruction. 544 if (!SeenUse) { 545 // We need to check use of the CRBit in successors. 546 for (auto &SuccMBB : MBB.successors()) 547 if (SuccMBB->isLiveIn(CRBit) || SuccMBB->isLiveIn(CRReg)) { 548 SeenUse = true; 549 break; 550 } 551 if (!SeenUse) 552 InstrsToErase.push_back(CRSetMI); 553 } 554 } 555 for (MachineInstr *MI : InstrsToErase) { 556 LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: "); 557 LLVM_DEBUG(MI->dump()); 558 MI->eraseFromParent(); 559 NumRemovedInPreEmit++; 560 } 561 return Changed; 562 } 563 }; 564 } 565 566 INITIALIZE_PASS(PPCPreEmitPeephole, DEBUG_TYPE, "PowerPC Pre-Emit Peephole", 567 false, false) 568 char PPCPreEmitPeephole::ID = 0; 569 570 FunctionPass *llvm::createPPCPreEmitPeepholePass() { 571 return new PPCPreEmitPeephole(); 572 } 573