| /dpdk/doc/guides/cryptodevs/ |
| H A D | dpaa_sec.rst | 10 hardware accelerator.
16 acceleration and offloading hardware. It combines functions previously
20 integrity checking, and a hardware random number generator. SEC performs
24 DPAA_SEC is one of the hardware resource in DPAA Architecture. More information
30 DPAA_SEC PMD also uses some of the other hardware resources like buffer pools,
31 queues, queue portals to store and to enqueue/dequeue data to the hardware SEC.
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| H A D | dpaa2_sec.rst | 10 hardware accelerator.
16 acceleration and offloading hardware. It combines functions previously
20 integrity checking, and a hardware random number generator. SEC performs
24 DPAA2_SEC is one of the hardware resource in DPAA2 Architecture. More information
28 portal to access the hardware object - DPSECI. The MC provides access to create,
31 DPAA2_SEC PMD also uses some of the other hardware resources like buffer pools,
32 queues, queue portals to store and to enqueue/dequeue data to the hardware SEC.
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| H A D | caam_jr.rst | 9 hardware accelerator. More information is available at:
17 acceleration and offloading hardware. It combines functions previously
21 integrity checking, and a hardware random number generator. SEC performs
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| H A D | ccp.rst | 11 CCP hardware engines on the platform. The CCP PMD provides poll mode crypto
12 driver support for the following hardware accelerator devices::
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| H A D | ionic.rst | 8 to hardware cryptographic blocks on AMD Pensando server adapters.
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| /dpdk/doc/guides/nics/ |
| H A D | gve.rst | 42 as a Queue Page List (QPL) in hardware (Google Hypervisor/GVE Backend) first.
45 and put this packet's offset in the QPL memory into hardware descriptors
46 so that hardware can get the packets data.
51 that driver can put packets' physical address into hardware descriptors.
56 driver can put packets' physical address into hardware descriptors.
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| H A D | octeon_ep.rst | 20 PMD may read the packet count directly from hardware registers
39 This module, octeon_drv, drives the physical function, initializes hardware,
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| H A D | pfe.rst | 28 PFE is a hardware programmable packet forwarding engine to provide
72 The HIF, PFE, MAC and PHY are the hardware blocks, the pfe.ko is a kernel
76 The PFE hardware supports one HIF (host interface) RX ring and one TX ring
83 hardware independent and register with the HIF client driver to transmit and
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| H A D | mana.rst | 25 (context initialization, hardware resources allocations)
43 that manage actual hardware initialization
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| H A D | nfb.rst | 42 Kernel modules manage initialization of hardware, allocation and
60 The PMD supports hardware timestamps of frame receipt on physical network interface. In order to use
61 the timestamps, the hardware timestamping unit must be enabled (follow the documentation of the NFB
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| H A D | enetfec.rst | 33 ENETFEC PMD is a hardware programmable packet forwarding engine
70 The MAC and PHY are the hardware blocks.
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| /dpdk/doc/guides/mldevs/ |
| H A D | cnxk.rst | 110 on CPU cores or hardware accelerators.
221 On platforms which don't support ML hardware acceleration through PCI device,
259 When enabled, firmware would mask the DPE non-fatal hardware errors as warnings.
336 **Enable hardware queue lock** (default ``0``)
339 to queue the requests to hardware queue.
343 Disable (default), use lock-free version of hardware enqueue function
345 To avoid race condition in request queuing to hardware,
349 Enable, use spin-lock version of hardware enqueue function for job queuing.
359 With the above configuration, spinlock version of hardware enqueue function is used
423 | 1 | Avg-HW-Latency | Average hardware latency |
[all …]
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| /dpdk/doc/guides/dmadevs/ |
| H A D | ioat.rst | 13 This PMD, when used on supported hardware, allows data copies, for example,
14 cloning packet data, to be accelerated by IOAT hardware rather than having to
21 presence of supported hardware. Running ``dpdk-devbind.py --status-dev dma``
23 list. For Intel\ |reg| IOAT devices, the hardware will often be listed as
28 Error handling is not supported by this driver on hardware prior to
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| H A D | odm.rst | 30 can be used to show the presence of supported hardware.
71 by a hardware register which can be configured as below::
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| /dpdk/doc/guides/windows_gsg/ |
| H A D | run_apps.rst | 50 by hardware PMDs.
67 NetUIO kernel-mode driver provides access to the device hardware resources.
68 It is mandatory for all hardware PMDs, except for mlx5 PMD.
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| /dpdk/doc/guides/rel_notes/ |
| H A D | release_2_0.rst | 30 .. note:: The software is intended to run on pre-release hardware and may contain unknown or unreso…
32 …iver is also pre-release and will be updated to a released version post hardware and base driver r…
33 …Should the official hardware release be made between DPDK releases an updated poll-mode driver wil…
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| /dpdk/lib/pcapng/ |
| H A D | rte_pcapng.h | 55 const char *osname, const char *hardware,
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| /dpdk/doc/guides/eventdevs/ |
| H A D | dlb2.rst | 8 hardware versions 2.0 and 2.5.
28 However, the DLB hardware is not a perfect match to the eventdev API. Some DLB
32 detailed understanding of the hardware, but these details are important when
41 directed queues, ports, credits, and other hardware resources. Some
140 DLB uses a hardware credit scheme to prevent software from overflowing hardware
142 a credit to enqueue an event, and hardware refills the ports with credits as the
196 replenished asynchronously by the DLB hardware.
202 credit scheme on top of the hardware credit scheme in order to comply with
205 The DLB's hardware scheme is local to a queue/pipeline stage: a port spends a
220 to enqueue if it lacks enough hardware credits to enqueue; load-balanced
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| /dpdk/doc/guides/testpmd_app_ug/ |
| H A D | intro.rst | 10 and also to access NIC hardware features such as Flow Director.
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| /dpdk/doc/guides/bbdevs/ |
| H A D | fpga_lte_fec.rst | 85 to VMs/Containers. The configuration involves allocating the number of hardware
112 - ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
121 - ``*l_load_balance``: hardware queues are load-balanced in a round-robin
126 If all hardware queues exceeds the watermark, no code blocks will be
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| H A D | fpga_5gnr_fec.rst | 95 to VMs/Containers. The configuration involves allocating the number of hardware
121 - ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
132 - ``*l_load_balance``: hardware queues are load-balanced in a round-robin
137 If all hardware queues exceeds the watermark, no code blocks will be
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| /dpdk/doc/guides/prog_guide/ |
| H A D | service_cores.rst | 18 For example, the Eventdev has hardware and software PMDs. Of these the software
19 PMD requires an lcore to perform the scheduling operations, while the hardware
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| /dpdk/doc/guides/sample_app_ug/ |
| H A D | vmdq_forwarding.rst | 9 The traffic splitting is performed in hardware by the VMDq feature of the Intel® 82599 and X710/XL7…
77 The VMDq hardware feature is configured at port initialization time by setting the appropriate valu…
110 the initialization of the port's RX and TX hardware rings is performed similarly to that
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| /dpdk/doc/guides/compressdevs/ |
| H A D | qat_comp.rst | 8 support for the following hardware accelerator devices:
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| /dpdk/doc/guides/platform/ |
| H A D | dpaa.rst | 61 If one is planning to use more than 1 Recv queue and hardware capability to
65 configuration will remain in the hardware till it is re-configured. This
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