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/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx9_asm_sop2.s3 s_add_u32 s5, s1, s2
33 s_add_u32 s5, s101, s2
36 s_add_u32 s5, flat_scratch_lo, s2
39 s_add_u32 s5, flat_scratch_hi, s2
42 s_add_u32 s5, vcc_lo, s2
45 s_add_u32 s5, vcc_hi, s2
48 s_add_u32 s5, ttmp15, s2
51 s_add_u32 s5, m0, s2
54 s_add_u32 s5, exec_lo, s2
57 s_add_u32 s5, exec_hi, s2
[all …]
H A Dgfx7_asm_sop2.s3 s_add_u32 s5, s1, s2
45 s_add_u32 s5, s103, s2
48 s_add_u32 s5, flat_scratch_lo, s2
51 s_add_u32 s5, flat_scratch_hi, s2
54 s_add_u32 s5, vcc_lo, s2
57 s_add_u32 s5, vcc_hi, s2
60 s_add_u32 s5, tba_lo, s2
63 s_add_u32 s5, tba_hi, s2
66 s_add_u32 s5, tma_lo, s2
69 s_add_u32 s5, tma_hi, s2
[all …]
H A Dgfx1150_asm_salu_float.s3 s_cvt_f32_i32 s5, s1
9 s_cvt_f32_i32 s5, s105
12 s_cvt_f32_i32 s5, s103
15 s_cvt_f32_i32 s5, vcc_lo
18 s_cvt_f32_i32 s5, vcc_hi
21 s_cvt_f32_i32 s5, ttmp11
24 s_cvt_f32_i32 s5, m0
27 s_cvt_f32_i32 s5, exec_lo
30 s_cvt_f32_i32 s5, exec_hi
33 s_cvt_f32_i32 s5, 0
[all …]
H A Dgfx8_asm_sop2.s3 s_add_u32 s5, s1, s2
45 s_add_u32 s5, s101, s2
48 s_add_u32 s5, flat_scratch_lo, s2
51 s_add_u32 s5, flat_scratch_hi, s2
54 s_add_u32 s5, vcc_lo, s2
57 s_add_u32 s5, vcc_hi, s2
60 s_add_u32 s5, tba_lo, s2
63 s_add_u32 s5, tba_hi, s2
66 s_add_u32 s5, tma_lo, s2
69 s_add_u32 s5, tma_hi, s2
[all …]
H A Dgfx8_asm_sop1.s3 s_mov_b32 s5, s1
45 s_mov_b32 s5, s101
48 s_mov_b32 s5, flat_scratch_lo
51 s_mov_b32 s5, flat_scratch_hi
54 s_mov_b32 s5, vcc_lo
57 s_mov_b32 s5, vcc_hi
60 s_mov_b32 s5, tba_lo
63 s_mov_b32 s5, tba_hi
66 s_mov_b32 s5, tma_lo
69 s_mov_b32 s5, tma_hi
[all …]
H A Dgfx7_asm_sop1.s3 s_mov_b32 s5, s1
45 s_mov_b32 s5, s103
48 s_mov_b32 s5, flat_scratch_lo
51 s_mov_b32 s5, flat_scratch_hi
54 s_mov_b32 s5, vcc_lo
57 s_mov_b32 s5, vcc_hi
60 s_mov_b32 s5, tba_lo
63 s_mov_b32 s5, tba_hi
66 s_mov_b32 s5, tma_lo
69 s_mov_b32 s5, tma_hi
[all …]
H A Dgfx9_asm_sop1.s3 s_mov_b32 s5, s1
33 s_mov_b32 s5, s101
36 s_mov_b32 s5, flat_scratch_lo
39 s_mov_b32 s5, flat_scratch_hi
42 s_mov_b32 s5, vcc_lo
45 s_mov_b32 s5, vcc_hi
48 s_mov_b32 s5, ttmp15
51 s_mov_b32 s5, m0
54 s_mov_b32 s5, exec_lo
57 s_mov_b32 s5, exec_hi
[all …]
H A Dgfx12_asm_smem.s37 s_load_i8 s5, s[2:3], s0
49 s_load_i8 s5, s[4:5], s0
52 s_load_i8 s5, s[100:101], s0
55 s_load_i8 s5, vcc, s0
58 s_load_i8 s5, s[2:3], s101
61 s_load_i8 s5, s[2:3], vcc_lo
64 s_load_i8 s5, s[2:3], vcc_hi
67 s_load_i8 s5, s[2:3], m0
70 s_load_i8 s5, s[2:3], 0x0
73 s_load_i8 s5,
[all...]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx9_sop2.txt3 # CHECK: s_add_u32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0x80]
30 # CHECK: s_add_u32 s5, s101, s2 ; encoding: [0x65,0x02,0x05,0x80]
33 # CHECK: s_add_u32 s5, flat_scratch_lo, s2 ; encoding: [0x66,0x02,0x05,0x80]
36 # CHECK: s_add_u32 s5, flat_scratch_hi, s2 ; encoding: [0x67,0x02,0x05,0x80]
39 # CHECK: s_add_u32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0x80]
42 # CHECK: s_add_u32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0x80]
45 # CHECK: s_add_u32 s5, m0, s2 ; encoding: [0x7c,0x02,0x05,0x80]
48 # CHECK: s_add_u32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0x80]
51 # CHECK: s_add_u32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0x80]
54 # CHECK: s_add_u32 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0x80]
[all …]
H A Dgfx1150_dasm_salu_float.txt3 # GFX1150: s_cvt_f32_i32 s5, s1 ; encoding: [0x01,0x64,0x85,0xbe]
9 # GFX1150: s_cvt_f32_i32 s5, s105 ; encoding: [0x69,0x64,0x85,0xbe]
12 # GFX1150: s_cvt_f32_i32 s5, s103 ; encoding: [0x67,0x64,0x85,0xbe]
15 # GFX1150: s_cvt_f32_i32 s5, vcc_lo ; encoding: [0x6a,0x64,0x85,0xbe]
18 # GFX1150: s_cvt_f32_i32 s5, vcc_hi ; encoding: [0x6b,0x64,0x85,0xbe]
21 # GFX1150: s_cvt_f32_i32 s5, ttmp11 ; encoding: [0x77,0x64,0x85,0xbe]
24 # GFX1150: s_cvt_f32_i32 s5, m0 ; encoding: [0x7d,0x64,0x85,0xbe]
27 # GFX1150: s_cvt_f32_i32 s5, exec_lo ; encoding: [0x7e,0x64,0x85,0xbe]
30 # GFX1150: s_cvt_f32_i32 s5, exec_hi ; encoding: [0x7f,0x64,0x85,0xbe]
33 # GFX1150: s_cvt_f32_i32 s5, 0 ; encoding: [0x80,0x64,0x85,0xbe]
[all …]
H A Dgfx8_sop2.txt3 # CHECK: s_add_u32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0x80]
45 # CHECK: s_add_u32 s5, s101, s2 ; encoding: [0x65,0x02,0x05,0x80]
48 # CHECK: s_add_u32 s5, flat_scratch_lo, s2 ; encoding: [0x66,0x02,0x05,0x80]
51 # CHECK: s_add_u32 s5, flat_scratch_hi, s2 ; encoding: [0x67,0x02,0x05,0x80]
54 # CHECK: s_add_u32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0x80]
57 # CHECK: s_add_u32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0x80]
60 # CHECK: s_add_u32 s5, tba_lo, s2 ; encoding: [0x6c,0x02,0x05,0x80]
63 # CHECK: s_add_u32 s5, tba_hi, s2 ; encoding: [0x6d,0x02,0x05,0x80]
66 # CHECK: s_add_u32 s5, tma_lo, s2 ; encoding: [0x6e,0x02,0x05,0x80]
69 # CHECK: s_add_u32 s5, tma_hi, s2 ; encoding: [0x6f,0x02,0x05,0x80]
[all …]
H A Dgfx9_sop1.txt3 # CHECK: s_mov_b32 s5, s1 ; encoding: [0x01,0x00,0x85,0xbe]
30 # CHECK: s_mov_b32 s5, s101 ; encoding: [0x65,0x00,0x85,0xbe]
33 # CHECK: s_mov_b32 s5, flat_scratch_lo ; encoding: [0x66,0x00,0x85,0xbe]
36 # CHECK: s_mov_b32 s5, flat_scratch_hi ; encoding: [0x67,0x00,0x85,0xbe]
39 # CHECK: s_mov_b32 s5, vcc_lo ; encoding: [0x6a,0x00,0x85,0xbe]
42 # CHECK: s_mov_b32 s5, vcc_hi ; encoding: [0x6b,0x00,0x85,0xbe]
45 # CHECK: s_mov_b32 s5, m0 ; encoding: [0x7c,0x00,0x85,0xbe]
48 # CHECK: s_mov_b32 s5, exec_lo ; encoding: [0x7e,0x00,0x85,0xbe]
51 # CHECK: s_mov_b32 s5, exec_hi ; encoding: [0x7f,0x00,0x85,0xbe]
54 # CHECK: s_mov_b32 s5, 0 ; encoding: [0x80,0x00,0x85,0xbe]
[all …]
H A Dgfx8_sop1.txt3 # CHECK: s_mov_b32 s5, s1 ; encoding: [0x01,0x00,0x85,0xbe]
45 # CHECK: s_mov_b32 s5, s101 ; encoding: [0x65,0x00,0x85,0xbe]
48 # CHECK: s_mov_b32 s5, flat_scratch_lo ; encoding: [0x66,0x00,0x85,0xbe]
51 # CHECK: s_mov_b32 s5, flat_scratch_hi ; encoding: [0x67,0x00,0x85,0xbe]
54 # CHECK: s_mov_b32 s5, vcc_lo ; encoding: [0x6a,0x00,0x85,0xbe]
57 # CHECK: s_mov_b32 s5, vcc_hi ; encoding: [0x6b,0x00,0x85,0xbe]
60 # CHECK: s_mov_b32 s5, tba_lo ; encoding: [0x6c,0x00,0x85,0xbe]
63 # CHECK: s_mov_b32 s5, tba_hi ; encoding: [0x6d,0x00,0x85,0xbe]
66 # CHECK: s_mov_b32 s5, tma_lo ; encoding: [0x6e,0x00,0x85,0xbe]
69 # CHECK: s_mov_b32 s5, tma_hi ; encoding: [0x6f,0x00,0x85,0xbe]
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Didiv-licm.ll20 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
21 ; GFX9-NEXT: s_mul_i32 s4, s4, s5
22 ; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
23 ; GFX9-NEXT: s_add_i32 s8, s5, s4
27 ; GFX9-NEXT: s_not_b32 s10, s5
28 ; GFX9-NEXT: s_mul_i32 s9, s6, s5
30 ; GFX9-NEXT: s_add_i32 s11, s5, 1
34 ; GFX9-NEXT: s_cselect_b32 s11, s11, s5
43 ; GFX9-NEXT: s_addc_u32 s5, s5,
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.image.atomic.dim.ll16 ; GFX6-NEXT: s_mov_b32 s3, s5
18 ; GFX6-NEXT: s_mov_b32 s5, s7
30 ; GFX8-NEXT: s_mov_b32 s3, s5
32 ; GFX8-NEXT: s_mov_b32 s5, s7
44 ; GFX900-NEXT: s_mov_b32 s3, s5
46 ; GFX900-NEXT: s_mov_b32 s5, s7
58 ; GFX90A-NEXT: s_mov_b32 s3, s5
60 ; GFX90A-NEXT: s_mov_b32 s5, s7
73 ; GFX10PLUS-NEXT: s_mov_b32 s3, s5
75 ; GFX10PLUS-NEXT: s_mov_b32 s5, s7
[all …]
H A Dllvm.amdgcn.image.store.2d.ll14 ; GFX6-NEXT: s_mov_b32 s3, s5
16 ; GFX6-NEXT: s_mov_b32 s5, s7
27 ; GFX8-NEXT: s_mov_b32 s3, s5
29 ; GFX8-NEXT: s_mov_b32 s5, s7
40 ; GFX10-NEXT: s_mov_b32 s3, s5
42 ; GFX10-NEXT: s_mov_b32 s5, s7
53 ; GFX11-NEXT: s_mov_b32 s3, s5
55 ; GFX11-NEXT: s_mov_b32 s5, s7
66 ; GFX12-NEXT: s_mov_b32 s3, s5
68 ; GFX12-NEXT: s_mov_b32 s5, s
[all...]
H A Dllvm.amdgcn.image.load.1d.ll15 ; GFX68-NEXT: s_mov_b32 s3, s5
17 ; GFX68-NEXT: s_mov_b32 s5, s7
29 ; GFX10-NEXT: s_mov_b32 s3, s5
31 ; GFX10-NEXT: s_mov_b32 s5, s7
43 ; NOPRT-NEXT: s_mov_b32 s3, s5
45 ; NOPRT-NEXT: s_mov_b32 s5, s7
57 ; GFX12-NEXT: s_mov_b32 s3, s5
59 ; GFX12-NEXT: s_mov_b32 s5, s7
75 ; GFX68-NEXT: s_mov_b32 s3, s5
77 ; GFX68-NEXT: s_mov_b32 s5, s7
[all …]
H A Dllvm.amdgcn.image.load.1d.d16.ll15 ; GFX8-UNPACKED-NEXT: s_mov_b32 s3, s5
17 ; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s7
29 ; GFX8-PACKED-NEXT: s_mov_b32 s3, s5
31 ; GFX8-PACKED-NEXT: s_mov_b32 s5, s7
43 ; GFX9-NEXT: s_mov_b32 s3, s5
45 ; GFX9-NEXT: s_mov_b32 s5, s7
57 ; GFX10PLUS-NEXT: s_mov_b32 s3, s5
59 ; GFX10PLUS-NEXT: s_mov_b32 s5, s7
71 ; GFX12-NEXT: s_mov_b32 s3, s5
73 ; GFX12-NEXT: s_mov_b32 s5, s7
[all …]
H A Dllvm.amdgcn.image.getresinfo.ll14 ; GFX6-NEXT: s_mov_b32 s3, s5
16 ; GFX6-NEXT: s_mov_b32 s5, s7
28 ; GFX8-NEXT: s_mov_b32 s3, s5
30 ; GFX8-NEXT: s_mov_b32 s5, s7
42 ; GFX10-NEXT: s_mov_b32 s3, s5
44 ; GFX10-NEXT: s_mov_b32 s5, s7
56 ; GFX12-NEXT: s_mov_b32 s3, s5
58 ; GFX12-NEXT: s_mov_b32 s5, s7
75 ; GFX6-NEXT: s_mov_b32 s3, s5
77 ; GFX6-NEXT: s_mov_b32 s5, s7
[all …]
H A Dllvm.amdgcn.image.atomic.dim.a16.ll13 ; GFX9-NEXT: s_mov_b32 s3, s5
15 ; GFX9-NEXT: s_mov_b32 s5, s7
27 ; GFX10-NEXT: s_mov_b32 s3, s5
29 ; GFX10-NEXT: s_mov_b32 s5, s7
41 ; GFX12-NEXT: s_mov_b32 s3, s5
43 ; GFX12-NEXT: s_mov_b32 s5, s7
61 ; GFX9-NEXT: s_mov_b32 s3, s5
63 ; GFX9-NEXT: s_mov_b32 s5, s7
75 ; GFX10-NEXT: s_mov_b32 s3, s5
77 ; GFX10-NEXT: s_mov_b32 s5, s
[all...]
/llvm-project/mlir/include/mlir/Dialect/Linalg/IR/
H A DLinalgNamedStructuredOps.yaml1339 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s0, s1, s2, s3)>
1344 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s4, s1, s5, s3)>
1349 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s0, s4, s2, s5)>
1352 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d0, d2, d3,
1354 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d1, d2, d4,
1356 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d0, d1, d3,
1416 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5, s6] -> (s0, s1, s2, s3, s4)>
1421 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5, s
[all...]
/llvm-project/llvm/test/CodeGen/VE/Scalar/
H A Datomicrmw-uinc-udec-wrap.ll19 ; CHECK-NEXT: or %s5, 0, %s4
20 ; CHECK-NEXT: and %s4, %s5, (32)0
28 ; CHECK-NEXT: and %s6, %s5, %s2
30 ; CHECK-NEXT: cas.w %s4, (%s1), %s5
31 ; CHECK-NEXT: brne.w %s4, %s5, .LBB0_1
56 ; CHECK-NEXT: or %s5, 0, %s4
57 ; CHECK-NEXT: and %s4, %s5, (32)0
65 ; CHECK-NEXT: and %s6, %s5, %s2
67 ; CHECK-NEXT: cas.w %s4, (%s1), %s5
68 ; CHECK-NEXT: brne.w %s4, %s5, .LBB1_1
[all …]
/llvm-project/llvm/test/CodeGen/VE/Vector/
H A Dvec_divrem.ll36 ; CHECK-NEXT: muls.l %s5, %s3, %s4
37 ; CHECK-NEXT: srl %s5, %s5, 32
38 ; CHECK-NEXT: muls.w.sx %s5, %s5, (56)0
39 ; CHECK-NEXT: subs.w.sx %s3, %s3, %s5
40 ; CHECK-NEXT: muls.l %s5, %s2, %s4
41 ; CHECK-NEXT: srl %s5, %s5, 32
42 ; CHECK-NEXT: muls.w.sx %s5, %s5, (56)0
43 ; CHECK-NEXT: subs.w.sx %s2, %s2, %s5
44 ; CHECK-NEXT: muls.l %s5, %s1, %s4
45 ; CHECK-NEXT: srl %s5, %s5, 32
[all …]
/llvm-project/llvm/test/MC/RISCV/
H A Drvzabha-valid.s30 # CHECK-ASM-AND-OBJ: amomax.b s7, s6, (s5)
32 amomax.b s7, s6, (s5)
33 # CHECK-ASM-AND-OBJ: amominu.b s6, s5, (s4)
35 amominu.b s6, s5, (s4)
36 # CHECK-ASM-AND-OBJ: amomaxu.b s5, s4, (s3)
38 amomaxu.b s5, s4, (s3)
58 # CHECK-ASM-AND-OBJ: amomax.b.aq s7, s6, (s5)
60 amomax.b.aq s7, s6, (s5)
61 # CHECK-ASM-AND-OBJ: amominu.b.aq s6, s5, (s4)
63 amominu.b.aq s6, s5, (s
[all...]
/llvm-project/llvm/test/tools/llvm-mca/AMDGPU/
H A Dgfx12-pseudo-scalar-trans.s11 v_s_rcp_f16 s5, s2
12 v_s_rsq_f16 s5, s4
13 v_s_sqrt_f16 s5, s5
41 # CHECK-NEXT: 1 7 1.00 U v_s_rcp_f16 s5, s2
42 # CHECK-NEXT: 1 7 1.00 U v_s_rsq_f16 s5, s4
43 # CHECK-NEXT: 1 7 1.00 U v_s_sqrt_f16 s5, s5
67 # CHECK-NEXT: - - - 1.00 - 1.00 - v_s_rcp_f16 s5, s2
68 # CHECK-NEXT: - - - 1.00 - 1.00 - v_s_rsq_f16 s5, s4
69 # CHECK-NEXT: - - - 1.00 - 1.00 - v_s_sqrt_f16 s5, s5
82 # CHECK-NEXT: [0,7] . . . . . . DeeeeeeE . . v_s_rcp_f16 s5, s2
[all …]

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