Lines Matching full:s5
20 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
21 ; GFX9-NEXT: s_mul_i32 s4, s4, s5
22 ; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
23 ; GFX9-NEXT: s_add_i32 s8, s5, s4
27 ; GFX9-NEXT: s_not_b32 s10, s5
28 ; GFX9-NEXT: s_mul_i32 s9, s6, s5
30 ; GFX9-NEXT: s_add_i32 s11, s5, 1
34 ; GFX9-NEXT: s_cselect_b32 s11, s11, s5
43 ; GFX9-NEXT: s_addc_u32 s5, s5, 0
68 ; GFX10-NEXT: s_mul_hi_u32 s5, s4, s2
70 ; GFX10-NEXT: s_add_i32 s8, s4, s5
75 ; GFX10-NEXT: s_not_b32 s10, s5
76 ; GFX10-NEXT: s_mul_i32 s9, s6, s5
79 ; GFX10-NEXT: s_add_i32 s11, s5, 1
82 ; GFX10-NEXT: s_cselect_b32 s11, s11, s5
92 ; GFX10-NEXT: s_addc_u32 s5, s5, 0
120 ; GFX11-NEXT: s_mul_hi_u32 s5, s4, s2
122 ; GFX11-NEXT: s_add_i32 s8, s4, s5
128 ; GFX11-NEXT: s_not_b32 s10, s5
129 ; GFX11-NEXT: s_mul_i32 s9, s6, s5
132 ; GFX11-NEXT: s_add_i32 s11, s5, 1
135 ; GFX11-NEXT: s_cselect_b32 s11, s11, s5
145 ; GFX11-NEXT: s_addc_u32 s5, s5, 0
184 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
185 ; GFX9-NEXT: s_mul_i32 s4, s4, s5
186 ; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
187 ; GFX9-NEXT: s_add_i32 s8, s5, s4
191 ; GFX9-NEXT: s_not_b32 s10, s5
192 ; GFX9-NEXT: s_mul_i32 s9, s6, s5
205 ; GFX9-NEXT: s_addc_u32 s5, s5, 0
230 ; GFX10-NEXT: s_mul_hi_u32 s5, s4, s2
232 ; GFX10-NEXT: s_add_i32 s8, s4, s5
236 ; GFX10-NEXT: s_not_b32 s9, s5
238 ; GFX10-NEXT: s_mul_i32 s10, s6, s5
252 ; GFX10-NEXT: s_addc_u32 s5, s5, 0
280 ; GFX11-NEXT: s_mul_hi_u32 s5, s4, s2
282 ; GFX11-NEXT: s_add_i32 s8, s4, s5
288 ; GFX11-NEXT: s_not_b32 s9, s5
289 ; GFX11-NEXT: s_mul_i32 s10, s6, s5
304 ; GFX11-NEXT: s_addc_u32 s5, s5, 0
339 ; GFX9-NEXT: s_sub_i32 s5, 0, s2
344 ; GFX9-NEXT: s_mul_i32 s5, s5, s6
345 ; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
346 ; GFX9-NEXT: s_add_i32 s5, s6, s5
350 ; GFX9-NEXT: s_mul_hi_u32 s6, s3, s5
386 ; GFX10-NEXT: v_readfirstlane_b32 s5, v0
388 ; GFX10-NEXT: s_mul_i32 s4, s4, s5
389 ; GFX10-NEXT: s_mul_hi_u32 s6, s5, s4
391 ; GFX10-NEXT: s_add_i32 s5, s5, s6
394 ; GFX10-NEXT: s_mul_hi_u32 s6, s4, s5
434 ; GFX11-NEXT: v_readfirstlane_b32 s5, v0
436 ; GFX11-NEXT: s_mul_i32 s4, s4, s5
438 ; GFX11-NEXT: s_mul_hi_u32 s6, s5, s4
440 ; GFX11-NEXT: s_add_i32 s5, s5, s6
445 ; GFX11-NEXT: s_mul_hi_u32 s6, s4, s5
499 ; GFX9-NEXT: v_readfirstlane_b32 s5, v0
500 ; GFX9-NEXT: s_mul_i32 s4, s4, s5
501 ; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
502 ; GFX9-NEXT: s_add_i32 s4, s5, s4
506 ; GFX9-NEXT: s_mul_hi_u32 s5, s3, s4
507 ; GFX9-NEXT: s_mul_i32 s5, s5, s2
508 ; GFX9-NEXT: s_sub_i32 s5, s3, s5
509 ; GFX9-NEXT: s_sub_i32 s6, s5, s2
510 ; GFX9-NEXT: s_cmp_ge_u32 s5, s2
511 ; GFX9-NEXT: s_cselect_b32 s5, s6, s5
512 ; GFX9-NEXT: s_sub_i32 s6, s5, s2
513 ; GFX9-NEXT: s_cmp_ge_u32 s5, s2
514 ; GFX9-NEXT: s_cselect_b32 s5, s6, s5
516 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
540 ; GFX10-NEXT: s_mul_hi_u32 s5, s4, s3
542 ; GFX10-NEXT: s_add_i32 s4, s4, s5
545 ; GFX10-NEXT: s_mul_hi_u32 s5, s3, s4
546 ; GFX10-NEXT: s_mul_i32 s5, s5, s2
547 ; GFX10-NEXT: s_sub_i32 s5, s3, s5
548 ; GFX10-NEXT: s_sub_i32 s6, s5, s2
549 ; GFX10-NEXT: s_cmp_ge_u32 s5, s2
550 ; GFX10-NEXT: s_cselect_b32 s5, s6, s5
551 ; GFX10-NEXT: s_sub_i32 s6, s5, s2
552 ; GFX10-NEXT: s_cmp_ge_u32 s5, s2
553 ; GFX10-NEXT: s_cselect_b32 s5, s6, s5
555 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
584 ; GFX11-NEXT: s_mul_hi_u32 s5, s4, s3
586 ; GFX11-NEXT: s_add_i32 s4, s4, s5
591 ; GFX11-NEXT: s_mul_hi_u32 s5, s3, s4
592 ; GFX11-NEXT: s_mul_i32 s5, s5, s2
594 ; GFX11-NEXT: s_sub_i32 s5, s3, s5
595 ; GFX11-NEXT: s_sub_i32 s6, s5, s2
596 ; GFX11-NEXT: s_cmp_ge_u32 s5, s2
597 ; GFX11-NEXT: s_cselect_b32 s5, s6, s5
599 ; GFX11-NEXT: s_sub_i32 s6, s5, s2
600 ; GFX11-NEXT: s_cmp_ge_u32 s5, s2
601 ; GFX11-NEXT: s_cselect_b32 s5, s6, s5
603 ; GFX11-NEXT: v_mov_b32_e32 v1, s5
757 ; GFX9-NEXT: s_lshl_b32 s5, s4, 1
764 ; GFX9-NEXT: v_mov_b32_e32 v3, s5
790 ; GFX10-NEXT: s_lshl_b32 s5, s4, 1
797 ; GFX10-NEXT: v_mov_b32_e32 v3, s5
824 ; GFX11-NEXT: s_lshl_b32 s5, s4, 1
834 ; GFX11-NEXT: v_mov_b32_e32 v3, s5
886 ; GFX9-NEXT: s_and_b32 s5, 0xffff, s3
889 ; GFX9-NEXT: s_lshl_b32 s4, s5, 1
890 ; GFX9-NEXT: s_and_b32 s5, s3, 0xffff
892 ; GFX9-NEXT: s_cmpk_eq_i32 s5, 0x400
919 ; GFX10-NEXT: v_cmp_ge_f32_e64 s5, |v2|, |v0|
921 ; GFX10-NEXT: s_and_b32 s5, s5, exec_lo
923 ; GFX10-NEXT: s_and_b32 s5, 0xffff, s3
925 ; GFX10-NEXT: s_lshl_b32 s5, s5, 1
927 ; GFX10-NEXT: v_mov_b32_e32 v3, s5
961 ; GFX11-NEXT: v_cmp_ge_f32_e64 s5, |v2|, |v0|
964 ; GFX11-NEXT: s_and_b32 s5, s5, exec_lo
966 ; GFX11-NEXT: s_and_b32 s5, 0xffff, s3
968 ; GFX11-NEXT: s_lshl_b32 s5, s5, 1
970 ; GFX11-NEXT: v_mov_b32_e32 v3, s5
1021 ; GFX9-NEXT: s_and_b32 s5, 0xffff, s3
1023 ; GFX9-NEXT: s_lshl_b32 s4, s5, 1
1024 ; GFX9-NEXT: s_and_b32 s5, s3, 0xffff
1026 ; GFX9-NEXT: s_cmpk_eq_i32 s5, 0x400
1048 ; GFX10-NEXT: s_xor_b32 s5, s4, s2
1049 ; GFX10-NEXT: s_ashr_i32 s5, s5, 30
1050 ; GFX10-NEXT: s_or_b32 s5, s5, 1
1057 ; GFX10-NEXT: s_cselect_b32 s5, s5, 0
1058 ; GFX10-NEXT: v_add_nc_u32_e32 v2, s5, v2
1059 ; GFX10-NEXT: s_and_b32 s5, 0xffff, s3
1061 ; GFX10-NEXT: s_lshl_b32 s5, s5, 1
1063 ; GFX10-NEXT: v_mov_b32_e32 v3, s5
1089 ; GFX11-NEXT: s_xor_b32 s5, s4, s2
1090 ; GFX11-NEXT: s_ashr_i32 s5, s5, 30
1092 ; GFX11-NEXT: s_or_b32 s5, s5, 1
1102 ; GFX11-NEXT: s_cselect_b32 s5, s5, 0
1104 ; GFX11-NEXT: v_add_nc_u32_e32 v2, s5, v2
1105 ; GFX11-NEXT: s_and_b32 s5, 0xffff, s3
1107 ; GFX11-NEXT: s_lshl_b32 s5, s5, 1
1110 ; GFX11-NEXT: v_mov_b32_e32 v3, s5