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/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dmve-fmas.ll22 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
24 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
67 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
69 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
112 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
114 ; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
225 ; CHECK-MVE-NEXT: vmovx.f16 s4, s14
229 ; CHECK-MVE-NEXT: vmla.f16 s2, s14, s6
403 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
405 ; CHECK-MVE-NEXT: vcmp.f16 s14, #
[all...]
H A Dmve-vld3.ll45 ; CHECK-NEXT: vmov.f32 s14, s3
80 ; CHECK-NEXT: vmov.f32 s14, s3
99 ; CHECK-NEXT: vmov.f32 s19, s14
133 ; CHECK-NEXT: vmov.f32 s14, s3
151 ; CHECK-NEXT: vmov.f32 s19, s14
171 ; CHECK-NEXT: vmov.f32 s8, s14
182 ; CHECK-NEXT: vmov.f32 s30, s14
191 ; CHECK-NEXT: vmov.f32 s14, s20
306 ; CHECK-NEXT: vmov.f32 s7, s14
316 ; CHECK-NEXT: vmovx.f16 s8, s14
[all …]
H A Dmve-vcmpf.ll21 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
61 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
98 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
134 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
170 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
206 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
246 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
273 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
311 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
347 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s1
[all...]
H A Dmve-vcmpfr.ll21 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
64 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
104 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
143 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
182 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
221 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
264 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
294 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
335 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
374 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s1
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dcallee-special-input-sgprs-fixed-abi.ll145 ; GCN: ; use s14
166 ; GCN: ; use s14
179 ; GCN: ; use s14
190 ; GCN: ; use s14
235 ; GCN: s_mov_b32 s14, s7
251 ; GCN-NOT: s14
254 ; GCN-NOT: s14
270 ; GCN: s_mov_b32 s14, s8
286 ; GCN-NEXT: s_mov_b32 s14, s7
303 ; GCN: s_mov_b32 s14, s
[all...]
H A Di1-copy-from-loop.ll7 ; SI-NEXT: s_mov_b32 s14, 0
25 ; SI-NEXT: s_cmp_lt_u32 s14, 4
28 ; SI-NEXT: s_cmp_gt_u32 s14, 3
32 ; SI-NEXT: v_mov_b32_e32 v1, s14
42 ; SI-NEXT: s_add_i32 s14, s14, 1
H A Dfcmp.f16.ll14 ; SI-NEXT: s_mov_b32 s14, s10
40 ; VI-NEXT: s_mov_b32 s14, s6
65 ; GFX11-NEXT: s_mov_b32 s14, s10
90 ; GFX12-NEXT: s_mov_b32 s14, s10
126 ; SI-NEXT: s_mov_b32 s14, s10
152 ; VI-NEXT: s_mov_b32 s14, s6
177 ; GFX11-NEXT: s_mov_b32 s14, s10
203 ; GFX12-NEXT: s_mov_b32 s14, s10
244 ; SI-NEXT: s_mov_b32 s14, s10
270 ; VI-NEXT: s_mov_b32 s14, s
[all...]
H A Dv_madak_f16.ll13 ; SI-NEXT: s_mov_b32 s14, s6
39 ; VI-NEXT: s_mov_b32 s14, s6
62 ; GFX11-NEXT: s_mov_b32 s14, s10
105 ; SI-NEXT: s_mov_b32 s12, s14
107 ; SI-NEXT: s_mov_b32 s14, s2
144 ; VI-NEXT: s_mov_b32 s12, s14
146 ; VI-NEXT: s_mov_b32 s14, s2
183 ; GFX11-NEXT: s_mov_b32 s20, s14
H A Dllvm.fmuladd.f16.ll20 ; SI-NEXT: s_mov_b32 s14, s10
54 ; VI-FLUSH-NEXT: s_mov_b32 s14, s10
82 ; VI-DENORM-NEXT: s_mov_b32 s14, s10
121 ; GFX10-FLUSH-NEXT: s_mov_b32 s12, s14
123 ; GFX10-FLUSH-NEXT: s_mov_b32 s14, s2
151 ; GFX10-DENORM-NEXT: s_mov_b32 s20, s14
168 ; GFX11-FLUSH-NEXT: s_mov_b32 s14, s10
199 ; GFX11-DENORM-NEXT: s_mov_b32 s14, s10
240 ; SI-NEXT: s_mov_b32 s14, s6
266 ; VI-FLUSH-NEXT: s_mov_b32 s14, s
[all...]
H A Dllvm.amdgcn.image.gather4.a16.dim.ll12 ; GFX9-NEXT: s_mov_b32 s14, 0x5040100
13 ; GFX9-NEXT: v_perm_b32 v0, v1, v0, s14
48 ; GFX9-NEXT: s_mov_b32 s14, 0x5040100
49 ; GFX9-NEXT: v_perm_b32 v1, v1, v0, s14
84 ; GFX9-NEXT: s_mov_b32 s14, 0x5040100
85 ; GFX9-NEXT: v_perm_b32 v1, v1, v0, s14
120 ; GFX9-NEXT: s_mov_b32 s14, 0x5040100
121 ; GFX9-NEXT: v_perm_b32 v1, v2, v1, s14
156 ; GFX9-NEXT: s_mov_b32 s14, 0x5040100
157 ; GFX9-NEXT: v_perm_b32 v1, v1, v0, s14
[all...]
H A Dfmin3.ll14 ; SI-NEXT: s_mov_b32 s14, s10
44 ; VI-NEXT: s_mov_b32 s14, s10
83 ; GFX9-NEXT: s_mov_b32 s12, s14
85 ; GFX9-NEXT: s_mov_b32 s14, s2
104 ; GFX11-NEXT: s_mov_b32 s14, s10
134 ; GFX12-NEXT: s_mov_b32 s14, s10
174 ; SI-NEXT: s_mov_b32 s14, s10
204 ; VI-NEXT: s_mov_b32 s14, s10
243 ; GFX9-NEXT: s_mov_b32 s12, s14
245 ; GFX9-NEXT: s_mov_b32 s14, s
[all...]
H A Dfmax3.ll14 ; SI-NEXT: s_mov_b32 s14, s10
44 ; VI-NEXT: s_mov_b32 s14, s10
83 ; GFX9-NEXT: s_mov_b32 s12, s14
85 ; GFX9-NEXT: s_mov_b32 s14, s2
104 ; GFX11-NEXT: s_mov_b32 s14, s10
134 ; GFX12-NEXT: s_mov_b32 s14, s10
174 ; SI-NEXT: s_mov_b32 s14, s10
204 ; VI-NEXT: s_mov_b32 s14, s10
243 ; GFX9-NEXT: s_mov_b32 s12, s14
245 ; GFX9-NEXT: s_mov_b32 s14, s
[all...]
H A Dsgpr-spill-no-vgprs.ll31 ; GCN-NEXT: v_writelane_b32 v22, s14, 6
50 ; GCN-NEXT: v_writelane_b32 v22, s14, 22
69 ; GCN-NEXT: v_writelane_b32 v22, s14, 38
88 ; GCN-NEXT: v_writelane_b32 v22, s14, 54
129 ; GCN-NEXT: v_readlane_b32 s14, v23, 10
151 ; GCN-NEXT: v_readlane_b32 s14, v23, 26
170 ; GCN-NEXT: v_readlane_b32 s14, v23, 42
185 ; GCN-NEXT: v_readlane_b32 s14, v23, 54
/llvm-project/polly/lib/External/isl/test_inputs/codegen/cloog/
H A Dusvd_e_t.c89 S14(8, 2, c2);
92 S14(8, 2, -2);
96 S14(8, 2, -1);
99 S14(8, 2, 0);
105 S14(8, 3, c2);
109 S14(8, 3, -1);
111 S14(8, 3, 0);
116 S14(8, 4, c2);
120 S14(8, 4, -1);
125 S14(8, 4, 0);
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.image.gather4.a16.dim.ll33 ; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
49 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
56 ; GFX12-NEXT: s_mov_b32 s14, exec_lo
72 ; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
107 ; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
123 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
130 ; GFX12-NEXT: s_mov_b32 s14, exec_lo
146 ; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14
181 ; GFX10NSA-NEXT: s_mov_b32 s14, exec_lo
197 ; GFX10NSA-NEXT: s_and_b32 exec_lo, exec_lo, s14
[all...]
H A Dinsertelement.ll600 ; GPRIDX-NEXT: s_mov_b32 s12, s14
602 ; GPRIDX-NEXT: s_mov_b32 s14, s16
624 ; GFX10PLUS-NEXT: s_mov_b32 s12, s14
626 ; GFX10PLUS-NEXT: s_mov_b32 s14, s16
650 ; GPRIDX-NEXT: s_mov_b32 s12, s14
652 ; GPRIDX-NEXT: s_mov_b32 s14, s16
674 ; GFX10PLUS-NEXT: s_mov_b32 s12, s14
676 ; GFX10PLUS-NEXT: s_mov_b32 s14, s16
691 ; GPRIDX-NEXT: s_mov_b32 s14, 0
712 ; GPRIDX-NEXT: v_mov_b32_e32 v13, s14
[all...]
/llvm-project/compiler-rt/lib/builtins/arm/
H A Dsubsf3vfp.S24 vmov s14, r0 // move first param from r0 into float register
26 vsub.f32 s14, s14, s15
27 vmov r0, s14 // move result back to r0
H A Daddsf3vfp.S23 vmov s14, r0 // move first param from r0 into float register
25 vadd.f32 s14, s14, s15
26 vmov r0, s14 // move result back to r0
/llvm-project/llvm/test/TableGen/
H A DConcatenatedSubregs.td46 def S14 : MyReg<"s14">;
58 def D7 : MyReg<"d7", [S14, S15]>;
85 // CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
133 // CHECK-NEXT: SubReg ssub4 = S14
/llvm-project/llvm/test/CodeGen/VE/Scalar/
H A Dstackframe_align.ll18 ; CHECK-NEXT: ld %s61, 24(, %s14)
41 ; CHECKFP-NEXT: ld %s61, 24(, %s14)
73 ; CHECK-NEXT: ld %s61, 24(, %s14)
96 ; CHECKFP-NEXT: ld %s61, 24(, %s14)
128 ; CHECK-NEXT: ld %s61, 24(, %s14)
151 ; CHECKFP-NEXT: ld %s61, 24(, %s14)
188 ; CHECK-NEXT: ld %s61, 24(, %s14)
214 ; CHECKFP-NEXT: ld %s61, 24(, %s14)
251 ; CHECK-NEXT: ld %s61, 24(, %s14)
277 ; CHECKFP-NEXT: ld %s61, 24(, %s14)
[all …]
H A Dstackframe_size.ll25 ; CHECK-NEXT: ld %s61, 24(, %s14)
52 ; CHECK-NEXT: ld %s61, 24(, %s14)
79 ; CHECK-NEXT: ld %s61, 24(, %s14)
106 ; CHECK-NEXT: ld %s61, 24(, %s14)
133 ; CHECK-NEXT: ld %s61, 24(, %s14)
160 ; CHECK-NEXT: ld %s61, 24(, %s14)
189 ; CHECK-NEXT: ld %s61, 24(, %s14)
/llvm-project/lldb/test/API/arm/emulation/new-test-files/
H A Dtest-vpush-3-thumb.dat2 assembly_string="vpush {s11, s12, s13, s14}"
38 s14=0x00000000
91 s14=0x00000000
H A Dtest-vpop-3-thumb.dat2 assembly_string="vpop {s11, s12, s13, s14}"
48 s14=0x00000000
101 s14=0x00000001
/llvm-project/llvm/test/CodeGen/ARM/
H A Dcmse-harden-entry-arguments.ll29 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
61 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
93 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
125 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
161 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
193 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
225 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
254 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
282 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
323 ; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s1…
[all …]
/llvm-project/llvm/test/MC/AArch64/
H A Dneon-scalar-shift-imm.s73 sqshl s14, s17, #22
78 // CHECK: sqshl s14, s17, #22 // encoding: [0x2e,0x76,0x36,0x5f]
86 uqshl s14, s19, #18
91 // CHECK: uqshl s14, s19, #18 // encoding: [0x6e,0x76,0x32,0x7f]
99 sqshlu s16, s14, #25
104 // CHECK: sqshlu s16, s14, #25 // encoding: [0xd0,0x65,0x39,0x7f]
136 uqshrn h10, s14, #5
140 // CHECK: uqshrn h10, s14, #5 // encoding: [0xca,0x95,0x1b,0x7f]
169 sqshrun h20, s14, #3
173 // CHECK: sqshrun h20, s14, #3 // encoding: [0xd4,0x85,0x1d,0x7f]

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