1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE 3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP 4 5define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 6; CHECK-MVE-LABEL: vcmp_oeq_v4f32: 7; CHECK-MVE: @ %bb.0: @ %entry 8; CHECK-MVE-NEXT: vcmp.f32 s0, s4 9; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 10; CHECK-MVE-NEXT: vcmp.f32 s3, s4 11; CHECK-MVE-NEXT: cset r0, eq 12; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 13; CHECK-MVE-NEXT: vcmp.f32 s1, s4 14; CHECK-MVE-NEXT: cset r1, eq 15; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 16; CHECK-MVE-NEXT: vcmp.f32 s2, s4 17; CHECK-MVE-NEXT: cset r2, eq 18; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 19; CHECK-MVE-NEXT: cset r3, eq 20; CHECK-MVE-NEXT: cmp r3, #0 21; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 22; CHECK-MVE-NEXT: cmp r2, #0 23; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 24; CHECK-MVE-NEXT: cmp r1, #0 25; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 26; CHECK-MVE-NEXT: cmp r0, #0 27; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 28; CHECK-MVE-NEXT: bx lr 29; 30; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32: 31; CHECK-MVEFP: @ %bb.0: @ %entry 32; CHECK-MVEFP-NEXT: vmov r0, s4 33; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, r0 34; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 35; CHECK-MVEFP-NEXT: bx lr 36entry: 37 %i = insertelement <4 x float> undef, float %src2, i32 0 38 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 39 %c = fcmp oeq <4 x float> %src, %sp 40 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 41 ret <4 x float> %s 42} 43 44define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 45; CHECK-MVE-LABEL: vcmp_one_v4f32: 46; CHECK-MVE: @ %bb.0: @ %entry 47; CHECK-MVE-NEXT: vcmp.f32 s0, s4 48; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 49; CHECK-MVE-NEXT: vcmp.f32 s3, s4 50; CHECK-MVE-NEXT: cset r0, mi 51; CHECK-MVE-NEXT: csinc r0, r0, zr, le 52; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 53; CHECK-MVE-NEXT: vcmp.f32 s1, s4 54; CHECK-MVE-NEXT: cset r1, mi 55; CHECK-MVE-NEXT: csinc r1, r1, zr, le 56; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 57; CHECK-MVE-NEXT: vcmp.f32 s2, s4 58; CHECK-MVE-NEXT: cset r2, mi 59; CHECK-MVE-NEXT: csinc r2, r2, zr, le 60; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 61; CHECK-MVE-NEXT: cset r3, mi 62; CHECK-MVE-NEXT: csinc r3, r3, zr, le 63; CHECK-MVE-NEXT: cmp r3, #0 64; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 65; CHECK-MVE-NEXT: cmp r2, #0 66; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 67; CHECK-MVE-NEXT: cmp r1, #0 68; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 69; CHECK-MVE-NEXT: cmp r0, #0 70; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 71; CHECK-MVE-NEXT: bx lr 72; 73; CHECK-MVEFP-LABEL: vcmp_one_v4f32: 74; CHECK-MVEFP: @ %bb.0: @ %entry 75; CHECK-MVEFP-NEXT: vmov r0, s4 76; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0 77; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0 78; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 79; CHECK-MVEFP-NEXT: bx lr 80entry: 81 %i = insertelement <4 x float> undef, float %src2, i32 0 82 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 83 %c = fcmp one <4 x float> %src, %sp 84 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 85 ret <4 x float> %s 86} 87 88define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 89; CHECK-MVE-LABEL: vcmp_ogt_v4f32: 90; CHECK-MVE: @ %bb.0: @ %entry 91; CHECK-MVE-NEXT: vcmp.f32 s0, s4 92; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 93; CHECK-MVE-NEXT: vcmp.f32 s3, s4 94; CHECK-MVE-NEXT: cset r0, gt 95; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 96; CHECK-MVE-NEXT: vcmp.f32 s1, s4 97; CHECK-MVE-NEXT: cset r1, gt 98; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 99; CHECK-MVE-NEXT: vcmp.f32 s2, s4 100; CHECK-MVE-NEXT: cset r2, gt 101; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 102; CHECK-MVE-NEXT: cset r3, gt 103; CHECK-MVE-NEXT: cmp r3, #0 104; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 105; CHECK-MVE-NEXT: cmp r2, #0 106; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 107; CHECK-MVE-NEXT: cmp r1, #0 108; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 109; CHECK-MVE-NEXT: cmp r0, #0 110; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 111; CHECK-MVE-NEXT: bx lr 112; 113; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32: 114; CHECK-MVEFP: @ %bb.0: @ %entry 115; CHECK-MVEFP-NEXT: vmov r0, s4 116; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 117; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 118; CHECK-MVEFP-NEXT: bx lr 119entry: 120 %i = insertelement <4 x float> undef, float %src2, i32 0 121 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 122 %c = fcmp ogt <4 x float> %src, %sp 123 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 124 ret <4 x float> %s 125} 126 127define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 128; CHECK-MVE-LABEL: vcmp_oge_v4f32: 129; CHECK-MVE: @ %bb.0: @ %entry 130; CHECK-MVE-NEXT: vcmp.f32 s0, s4 131; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 132; CHECK-MVE-NEXT: vcmp.f32 s3, s4 133; CHECK-MVE-NEXT: cset r0, ge 134; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 135; CHECK-MVE-NEXT: vcmp.f32 s1, s4 136; CHECK-MVE-NEXT: cset r1, ge 137; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 138; CHECK-MVE-NEXT: vcmp.f32 s2, s4 139; CHECK-MVE-NEXT: cset r2, ge 140; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 141; CHECK-MVE-NEXT: cset r3, ge 142; CHECK-MVE-NEXT: cmp r3, #0 143; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 144; CHECK-MVE-NEXT: cmp r2, #0 145; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 146; CHECK-MVE-NEXT: cmp r1, #0 147; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 148; CHECK-MVE-NEXT: cmp r0, #0 149; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 150; CHECK-MVE-NEXT: bx lr 151; 152; CHECK-MVEFP-LABEL: vcmp_oge_v4f32: 153; CHECK-MVEFP: @ %bb.0: @ %entry 154; CHECK-MVEFP-NEXT: vmov r0, s4 155; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 156; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 157; CHECK-MVEFP-NEXT: bx lr 158entry: 159 %i = insertelement <4 x float> undef, float %src2, i32 0 160 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 161 %c = fcmp oge <4 x float> %src, %sp 162 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 163 ret <4 x float> %s 164} 165 166define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 167; CHECK-MVE-LABEL: vcmp_olt_v4f32: 168; CHECK-MVE: @ %bb.0: @ %entry 169; CHECK-MVE-NEXT: vcmp.f32 s0, s4 170; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 171; CHECK-MVE-NEXT: vcmp.f32 s3, s4 172; CHECK-MVE-NEXT: cset r0, mi 173; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 174; CHECK-MVE-NEXT: vcmp.f32 s1, s4 175; CHECK-MVE-NEXT: cset r1, mi 176; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 177; CHECK-MVE-NEXT: vcmp.f32 s2, s4 178; CHECK-MVE-NEXT: cset r2, mi 179; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 180; CHECK-MVE-NEXT: cset r3, mi 181; CHECK-MVE-NEXT: cmp r3, #0 182; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 183; CHECK-MVE-NEXT: cmp r2, #0 184; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 185; CHECK-MVE-NEXT: cmp r1, #0 186; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 187; CHECK-MVE-NEXT: cmp r0, #0 188; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 189; CHECK-MVE-NEXT: bx lr 190; 191; CHECK-MVEFP-LABEL: vcmp_olt_v4f32: 192; CHECK-MVEFP: @ %bb.0: @ %entry 193; CHECK-MVEFP-NEXT: vmov r0, s4 194; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 195; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 196; CHECK-MVEFP-NEXT: bx lr 197entry: 198 %i = insertelement <4 x float> undef, float %src2, i32 0 199 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 200 %c = fcmp olt <4 x float> %src, %sp 201 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 202 ret <4 x float> %s 203} 204 205define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 206; CHECK-MVE-LABEL: vcmp_ole_v4f32: 207; CHECK-MVE: @ %bb.0: @ %entry 208; CHECK-MVE-NEXT: vcmp.f32 s0, s4 209; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 210; CHECK-MVE-NEXT: vcmp.f32 s3, s4 211; CHECK-MVE-NEXT: cset r0, ls 212; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 213; CHECK-MVE-NEXT: vcmp.f32 s1, s4 214; CHECK-MVE-NEXT: cset r1, ls 215; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 216; CHECK-MVE-NEXT: vcmp.f32 s2, s4 217; CHECK-MVE-NEXT: cset r2, ls 218; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 219; CHECK-MVE-NEXT: cset r3, ls 220; CHECK-MVE-NEXT: cmp r3, #0 221; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 222; CHECK-MVE-NEXT: cmp r2, #0 223; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 224; CHECK-MVE-NEXT: cmp r1, #0 225; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 226; CHECK-MVE-NEXT: cmp r0, #0 227; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 228; CHECK-MVE-NEXT: bx lr 229; 230; CHECK-MVEFP-LABEL: vcmp_ole_v4f32: 231; CHECK-MVEFP: @ %bb.0: @ %entry 232; CHECK-MVEFP-NEXT: vmov r0, s4 233; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 234; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 235; CHECK-MVEFP-NEXT: bx lr 236entry: 237 %i = insertelement <4 x float> undef, float %src2, i32 0 238 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 239 %c = fcmp ole <4 x float> %src, %sp 240 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 241 ret <4 x float> %s 242} 243 244define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 245; CHECK-MVE-LABEL: vcmp_ueq_v4f32: 246; CHECK-MVE: @ %bb.0: @ %entry 247; CHECK-MVE-NEXT: vcmp.f32 s0, s4 248; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 249; CHECK-MVE-NEXT: vcmp.f32 s3, s4 250; CHECK-MVE-NEXT: cset r0, eq 251; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 252; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 253; CHECK-MVE-NEXT: vcmp.f32 s1, s4 254; CHECK-MVE-NEXT: cset r1, eq 255; CHECK-MVE-NEXT: csinc r1, r1, zr, vc 256; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 257; CHECK-MVE-NEXT: vcmp.f32 s2, s4 258; CHECK-MVE-NEXT: cset r2, eq 259; CHECK-MVE-NEXT: csinc r2, r2, zr, vc 260; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 261; CHECK-MVE-NEXT: cset r3, eq 262; CHECK-MVE-NEXT: csinc r3, r3, zr, vc 263; CHECK-MVE-NEXT: cmp r3, #0 264; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 265; CHECK-MVE-NEXT: cmp r2, #0 266; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 267; CHECK-MVE-NEXT: cmp r1, #0 268; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 269; CHECK-MVE-NEXT: cmp r0, #0 270; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 271; CHECK-MVE-NEXT: bx lr 272; 273; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32: 274; CHECK-MVEFP: @ %bb.0: @ %entry 275; CHECK-MVEFP-NEXT: vmov r0, s4 276; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0 277; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0 278; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 279; CHECK-MVEFP-NEXT: bx lr 280entry: 281 %i = insertelement <4 x float> undef, float %src2, i32 0 282 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 283 %c = fcmp ueq <4 x float> %src, %sp 284 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 285 ret <4 x float> %s 286} 287 288define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 289; CHECK-MVE-LABEL: vcmp_une_v4f32: 290; CHECK-MVE: @ %bb.0: @ %entry 291; CHECK-MVE-NEXT: vcmp.f32 s2, s4 292; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 293; CHECK-MVE-NEXT: vcmp.f32 s1, s4 294; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 295; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 296; CHECK-MVE-NEXT: vcmp.f32 s3, s4 297; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 298; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 299; CHECK-MVE-NEXT: vcmp.f32 s0, s4 300; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 301; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 302; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 303; CHECK-MVE-NEXT: bx lr 304; 305; CHECK-MVEFP-LABEL: vcmp_une_v4f32: 306; CHECK-MVEFP: @ %bb.0: @ %entry 307; CHECK-MVEFP-NEXT: vmov r0, s4 308; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, r0 309; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 310; CHECK-MVEFP-NEXT: bx lr 311entry: 312 %i = insertelement <4 x float> undef, float %src2, i32 0 313 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 314 %c = fcmp une <4 x float> %src, %sp 315 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 316 ret <4 x float> %s 317} 318 319define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 320; CHECK-MVE-LABEL: vcmp_ugt_v4f32: 321; CHECK-MVE: @ %bb.0: @ %entry 322; CHECK-MVE-NEXT: vcmp.f32 s0, s4 323; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 324; CHECK-MVE-NEXT: vcmp.f32 s3, s4 325; CHECK-MVE-NEXT: cset r0, hi 326; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 327; CHECK-MVE-NEXT: vcmp.f32 s1, s4 328; CHECK-MVE-NEXT: cset r1, hi 329; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 330; CHECK-MVE-NEXT: vcmp.f32 s2, s4 331; CHECK-MVE-NEXT: cset r2, hi 332; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 333; CHECK-MVE-NEXT: cset r3, hi 334; CHECK-MVE-NEXT: cmp r3, #0 335; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 336; CHECK-MVE-NEXT: cmp r2, #0 337; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 338; CHECK-MVE-NEXT: cmp r1, #0 339; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 340; CHECK-MVE-NEXT: cmp r0, #0 341; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 342; CHECK-MVE-NEXT: bx lr 343; 344; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32: 345; CHECK-MVEFP: @ %bb.0: @ %entry 346; CHECK-MVEFP-NEXT: vmov r0, s4 347; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 348; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 349; CHECK-MVEFP-NEXT: bx lr 350entry: 351 %i = insertelement <4 x float> undef, float %src2, i32 0 352 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 353 %c = fcmp ugt <4 x float> %src, %sp 354 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 355 ret <4 x float> %s 356} 357 358define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 359; CHECK-MVE-LABEL: vcmp_uge_v4f32: 360; CHECK-MVE: @ %bb.0: @ %entry 361; CHECK-MVE-NEXT: vcmp.f32 s0, s4 362; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 363; CHECK-MVE-NEXT: vcmp.f32 s3, s4 364; CHECK-MVE-NEXT: cset r0, pl 365; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 366; CHECK-MVE-NEXT: vcmp.f32 s1, s4 367; CHECK-MVE-NEXT: cset r1, pl 368; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 369; CHECK-MVE-NEXT: vcmp.f32 s2, s4 370; CHECK-MVE-NEXT: cset r2, pl 371; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 372; CHECK-MVE-NEXT: cset r3, pl 373; CHECK-MVE-NEXT: cmp r3, #0 374; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 375; CHECK-MVE-NEXT: cmp r2, #0 376; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 377; CHECK-MVE-NEXT: cmp r1, #0 378; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 379; CHECK-MVE-NEXT: cmp r0, #0 380; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 381; CHECK-MVE-NEXT: bx lr 382; 383; CHECK-MVEFP-LABEL: vcmp_uge_v4f32: 384; CHECK-MVEFP: @ %bb.0: @ %entry 385; CHECK-MVEFP-NEXT: vmov r0, s4 386; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 387; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 388; CHECK-MVEFP-NEXT: bx lr 389entry: 390 %i = insertelement <4 x float> undef, float %src2, i32 0 391 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 392 %c = fcmp uge <4 x float> %src, %sp 393 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 394 ret <4 x float> %s 395} 396 397define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 398; CHECK-MVE-LABEL: vcmp_ult_v4f32: 399; CHECK-MVE: @ %bb.0: @ %entry 400; CHECK-MVE-NEXT: vcmp.f32 s0, s4 401; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 402; CHECK-MVE-NEXT: vcmp.f32 s3, s4 403; CHECK-MVE-NEXT: cset r0, lt 404; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 405; CHECK-MVE-NEXT: vcmp.f32 s1, s4 406; CHECK-MVE-NEXT: cset r1, lt 407; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 408; CHECK-MVE-NEXT: vcmp.f32 s2, s4 409; CHECK-MVE-NEXT: cset r2, lt 410; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 411; CHECK-MVE-NEXT: cset r3, lt 412; CHECK-MVE-NEXT: cmp r3, #0 413; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 414; CHECK-MVE-NEXT: cmp r2, #0 415; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 416; CHECK-MVE-NEXT: cmp r1, #0 417; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 418; CHECK-MVE-NEXT: cmp r0, #0 419; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 420; CHECK-MVE-NEXT: bx lr 421; 422; CHECK-MVEFP-LABEL: vcmp_ult_v4f32: 423; CHECK-MVEFP: @ %bb.0: @ %entry 424; CHECK-MVEFP-NEXT: vmov r0, s4 425; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 426; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 427; CHECK-MVEFP-NEXT: bx lr 428entry: 429 %i = insertelement <4 x float> undef, float %src2, i32 0 430 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 431 %c = fcmp ult <4 x float> %src, %sp 432 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 433 ret <4 x float> %s 434} 435 436define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 437; CHECK-MVE-LABEL: vcmp_ule_v4f32: 438; CHECK-MVE: @ %bb.0: @ %entry 439; CHECK-MVE-NEXT: vcmp.f32 s0, s4 440; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 441; CHECK-MVE-NEXT: vcmp.f32 s3, s4 442; CHECK-MVE-NEXT: cset r0, le 443; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 444; CHECK-MVE-NEXT: vcmp.f32 s1, s4 445; CHECK-MVE-NEXT: cset r1, le 446; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 447; CHECK-MVE-NEXT: vcmp.f32 s2, s4 448; CHECK-MVE-NEXT: cset r2, le 449; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 450; CHECK-MVE-NEXT: cset r3, le 451; CHECK-MVE-NEXT: cmp r3, #0 452; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 453; CHECK-MVE-NEXT: cmp r2, #0 454; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 455; CHECK-MVE-NEXT: cmp r1, #0 456; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 457; CHECK-MVE-NEXT: cmp r0, #0 458; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 459; CHECK-MVE-NEXT: bx lr 460; 461; CHECK-MVEFP-LABEL: vcmp_ule_v4f32: 462; CHECK-MVEFP: @ %bb.0: @ %entry 463; CHECK-MVEFP-NEXT: vmov r0, s4 464; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 465; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 466; CHECK-MVEFP-NEXT: bx lr 467entry: 468 %i = insertelement <4 x float> undef, float %src2, i32 0 469 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 470 %c = fcmp ule <4 x float> %src, %sp 471 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 472 ret <4 x float> %s 473} 474 475define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 476; CHECK-MVE-LABEL: vcmp_ord_v4f32: 477; CHECK-MVE: @ %bb.0: @ %entry 478; CHECK-MVE-NEXT: vcmp.f32 s0, s4 479; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 480; CHECK-MVE-NEXT: vcmp.f32 s3, s4 481; CHECK-MVE-NEXT: cset r0, vc 482; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 483; CHECK-MVE-NEXT: vcmp.f32 s1, s4 484; CHECK-MVE-NEXT: cset r1, vc 485; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 486; CHECK-MVE-NEXT: vcmp.f32 s2, s4 487; CHECK-MVE-NEXT: cset r2, vc 488; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 489; CHECK-MVE-NEXT: cset r3, vc 490; CHECK-MVE-NEXT: cmp r3, #0 491; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 492; CHECK-MVE-NEXT: cmp r2, #0 493; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 494; CHECK-MVE-NEXT: cmp r1, #0 495; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 496; CHECK-MVE-NEXT: cmp r0, #0 497; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 498; CHECK-MVE-NEXT: bx lr 499; 500; CHECK-MVEFP-LABEL: vcmp_ord_v4f32: 501; CHECK-MVEFP: @ %bb.0: @ %entry 502; CHECK-MVEFP-NEXT: vmov r0, s4 503; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0 504; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0 505; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 506; CHECK-MVEFP-NEXT: bx lr 507entry: 508 %i = insertelement <4 x float> undef, float %src2, i32 0 509 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 510 %c = fcmp ord <4 x float> %src, %sp 511 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 512 ret <4 x float> %s 513} 514 515define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 516; CHECK-MVE-LABEL: vcmp_uno_v4f32: 517; CHECK-MVE: @ %bb.0: @ %entry 518; CHECK-MVE-NEXT: vcmp.f32 s0, s4 519; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 520; CHECK-MVE-NEXT: vcmp.f32 s3, s4 521; CHECK-MVE-NEXT: cset r0, vs 522; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 523; CHECK-MVE-NEXT: vcmp.f32 s1, s4 524; CHECK-MVE-NEXT: cset r1, vs 525; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 526; CHECK-MVE-NEXT: vcmp.f32 s2, s4 527; CHECK-MVE-NEXT: cset r2, vs 528; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 529; CHECK-MVE-NEXT: cset r3, vs 530; CHECK-MVE-NEXT: cmp r3, #0 531; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 532; CHECK-MVE-NEXT: cmp r2, #0 533; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 534; CHECK-MVE-NEXT: cmp r1, #0 535; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 536; CHECK-MVE-NEXT: cmp r0, #0 537; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 538; CHECK-MVE-NEXT: bx lr 539; 540; CHECK-MVEFP-LABEL: vcmp_uno_v4f32: 541; CHECK-MVEFP: @ %bb.0: @ %entry 542; CHECK-MVEFP-NEXT: vmov r0, s4 543; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0 544; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0 545; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 546; CHECK-MVEFP-NEXT: bx lr 547entry: 548 %i = insertelement <4 x float> undef, float %src2, i32 0 549 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 550 %c = fcmp uno <4 x float> %src, %sp 551 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 552 ret <4 x float> %s 553} 554 555 556 557define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 558; CHECK-MVE-LABEL: vcmp_oeq_v8f16: 559; CHECK-MVE: @ %bb.0: @ %entry 560; CHECK-MVE-NEXT: vmovx.f16 s6, s0 561; CHECK-MVE-NEXT: vmovx.f16 s5, s12 562; CHECK-MVE-NEXT: vcmp.f16 s6, s4 563; CHECK-MVE-NEXT: vmovx.f16 s6, s8 564; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 565; CHECK-MVE-NEXT: vcmp.f16 s0, s4 566; CHECK-MVE-NEXT: cset r0, eq 567; CHECK-MVE-NEXT: cmp r0, #0 568; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 569; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 570; CHECK-MVE-NEXT: cset r0, eq 571; CHECK-MVE-NEXT: cmp r0, #0 572; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 573; CHECK-MVE-NEXT: vmovx.f16 s8, s13 574; CHECK-MVE-NEXT: vins.f16 s0, s6 575; CHECK-MVE-NEXT: vmovx.f16 s6, s1 576; CHECK-MVE-NEXT: vcmp.f16 s6, s4 577; CHECK-MVE-NEXT: vmovx.f16 s6, s9 578; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 579; CHECK-MVE-NEXT: vcmp.f16 s1, s4 580; CHECK-MVE-NEXT: cset r0, eq 581; CHECK-MVE-NEXT: cmp r0, #0 582; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 583; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 584; CHECK-MVE-NEXT: vmovx.f16 s8, s14 585; CHECK-MVE-NEXT: cset r0, eq 586; CHECK-MVE-NEXT: cmp r0, #0 587; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 588; CHECK-MVE-NEXT: vins.f16 s1, s6 589; CHECK-MVE-NEXT: vmovx.f16 s6, s2 590; CHECK-MVE-NEXT: vcmp.f16 s6, s4 591; CHECK-MVE-NEXT: vmovx.f16 s6, s10 592; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 593; CHECK-MVE-NEXT: vcmp.f16 s2, s4 594; CHECK-MVE-NEXT: cset r0, eq 595; CHECK-MVE-NEXT: cmp r0, #0 596; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 597; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 598; CHECK-MVE-NEXT: vmovx.f16 s8, s15 599; CHECK-MVE-NEXT: cset r0, eq 600; CHECK-MVE-NEXT: cmp r0, #0 601; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 602; CHECK-MVE-NEXT: vins.f16 s2, s6 603; CHECK-MVE-NEXT: vmovx.f16 s6, s3 604; CHECK-MVE-NEXT: vcmp.f16 s6, s4 605; CHECK-MVE-NEXT: vmovx.f16 s6, s11 606; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 607; CHECK-MVE-NEXT: vcmp.f16 s3, s4 608; CHECK-MVE-NEXT: cset r0, eq 609; CHECK-MVE-NEXT: cmp r0, #0 610; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 611; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 612; CHECK-MVE-NEXT: cset r0, eq 613; CHECK-MVE-NEXT: cmp r0, #0 614; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 615; CHECK-MVE-NEXT: vins.f16 s3, s6 616; CHECK-MVE-NEXT: bx lr 617; 618; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: 619; CHECK-MVEFP: @ %bb.0: @ %entry 620; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 621; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 622; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 623; CHECK-MVEFP-NEXT: bx lr 624entry: 625 %i = insertelement <8 x half> undef, half %src2, i32 0 626 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 627 %c = fcmp oeq <8 x half> %src, %sp 628 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 629 ret <8 x half> %s 630} 631 632define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 633; CHECK-MVE-LABEL: vcmp_one_v8f16: 634; CHECK-MVE: @ %bb.0: @ %entry 635; CHECK-MVE-NEXT: vmovx.f16 s6, s0 636; CHECK-MVE-NEXT: vmovx.f16 s5, s12 637; CHECK-MVE-NEXT: vcmp.f16 s6, s4 638; CHECK-MVE-NEXT: vmovx.f16 s6, s8 639; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 640; CHECK-MVE-NEXT: vcmp.f16 s0, s4 641; CHECK-MVE-NEXT: cset r0, mi 642; CHECK-MVE-NEXT: csinc r0, r0, zr, le 643; CHECK-MVE-NEXT: cmp r0, #0 644; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 645; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 646; CHECK-MVE-NEXT: cset r0, mi 647; CHECK-MVE-NEXT: csinc r0, r0, zr, le 648; CHECK-MVE-NEXT: cmp r0, #0 649; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 650; CHECK-MVE-NEXT: vmovx.f16 s8, s13 651; CHECK-MVE-NEXT: vins.f16 s0, s6 652; CHECK-MVE-NEXT: vmovx.f16 s6, s1 653; CHECK-MVE-NEXT: vcmp.f16 s6, s4 654; CHECK-MVE-NEXT: vmovx.f16 s6, s9 655; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 656; CHECK-MVE-NEXT: vcmp.f16 s1, s4 657; CHECK-MVE-NEXT: cset r0, mi 658; CHECK-MVE-NEXT: csinc r0, r0, zr, le 659; CHECK-MVE-NEXT: cmp r0, #0 660; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 661; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 662; CHECK-MVE-NEXT: vmovx.f16 s8, s14 663; CHECK-MVE-NEXT: cset r0, mi 664; CHECK-MVE-NEXT: csinc r0, r0, zr, le 665; CHECK-MVE-NEXT: cmp r0, #0 666; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 667; CHECK-MVE-NEXT: vins.f16 s1, s6 668; CHECK-MVE-NEXT: vmovx.f16 s6, s2 669; CHECK-MVE-NEXT: vcmp.f16 s6, s4 670; CHECK-MVE-NEXT: vmovx.f16 s6, s10 671; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 672; CHECK-MVE-NEXT: vcmp.f16 s2, s4 673; CHECK-MVE-NEXT: cset r0, mi 674; CHECK-MVE-NEXT: csinc r0, r0, zr, le 675; CHECK-MVE-NEXT: cmp r0, #0 676; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 677; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 678; CHECK-MVE-NEXT: vmovx.f16 s8, s15 679; CHECK-MVE-NEXT: cset r0, mi 680; CHECK-MVE-NEXT: csinc r0, r0, zr, le 681; CHECK-MVE-NEXT: cmp r0, #0 682; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 683; CHECK-MVE-NEXT: vins.f16 s2, s6 684; CHECK-MVE-NEXT: vmovx.f16 s6, s3 685; CHECK-MVE-NEXT: vcmp.f16 s6, s4 686; CHECK-MVE-NEXT: vmovx.f16 s6, s11 687; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 688; CHECK-MVE-NEXT: vcmp.f16 s3, s4 689; CHECK-MVE-NEXT: cset r0, mi 690; CHECK-MVE-NEXT: csinc r0, r0, zr, le 691; CHECK-MVE-NEXT: cmp r0, #0 692; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 693; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 694; CHECK-MVE-NEXT: cset r0, mi 695; CHECK-MVE-NEXT: csinc r0, r0, zr, le 696; CHECK-MVE-NEXT: cmp r0, #0 697; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 698; CHECK-MVE-NEXT: vins.f16 s3, s6 699; CHECK-MVE-NEXT: bx lr 700; 701; CHECK-MVEFP-LABEL: vcmp_one_v8f16: 702; CHECK-MVEFP: @ %bb.0: @ %entry 703; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 704; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 705; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0 706; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 707; CHECK-MVEFP-NEXT: bx lr 708entry: 709 %i = insertelement <8 x half> undef, half %src2, i32 0 710 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 711 %c = fcmp one <8 x half> %src, %sp 712 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 713 ret <8 x half> %s 714} 715 716define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 717; CHECK-MVE-LABEL: vcmp_ogt_v8f16: 718; CHECK-MVE: @ %bb.0: @ %entry 719; CHECK-MVE-NEXT: vmovx.f16 s6, s0 720; CHECK-MVE-NEXT: vmovx.f16 s5, s12 721; CHECK-MVE-NEXT: vcmp.f16 s6, s4 722; CHECK-MVE-NEXT: vmovx.f16 s6, s8 723; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 724; CHECK-MVE-NEXT: vcmp.f16 s0, s4 725; CHECK-MVE-NEXT: cset r0, gt 726; CHECK-MVE-NEXT: cmp r0, #0 727; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 728; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 729; CHECK-MVE-NEXT: cset r0, gt 730; CHECK-MVE-NEXT: cmp r0, #0 731; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 732; CHECK-MVE-NEXT: vmovx.f16 s8, s13 733; CHECK-MVE-NEXT: vins.f16 s0, s6 734; CHECK-MVE-NEXT: vmovx.f16 s6, s1 735; CHECK-MVE-NEXT: vcmp.f16 s6, s4 736; CHECK-MVE-NEXT: vmovx.f16 s6, s9 737; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 738; CHECK-MVE-NEXT: vcmp.f16 s1, s4 739; CHECK-MVE-NEXT: cset r0, gt 740; CHECK-MVE-NEXT: cmp r0, #0 741; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 742; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 743; CHECK-MVE-NEXT: vmovx.f16 s8, s14 744; CHECK-MVE-NEXT: cset r0, gt 745; CHECK-MVE-NEXT: cmp r0, #0 746; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 747; CHECK-MVE-NEXT: vins.f16 s1, s6 748; CHECK-MVE-NEXT: vmovx.f16 s6, s2 749; CHECK-MVE-NEXT: vcmp.f16 s6, s4 750; CHECK-MVE-NEXT: vmovx.f16 s6, s10 751; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 752; CHECK-MVE-NEXT: vcmp.f16 s2, s4 753; CHECK-MVE-NEXT: cset r0, gt 754; CHECK-MVE-NEXT: cmp r0, #0 755; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 756; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 757; CHECK-MVE-NEXT: vmovx.f16 s8, s15 758; CHECK-MVE-NEXT: cset r0, gt 759; CHECK-MVE-NEXT: cmp r0, #0 760; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 761; CHECK-MVE-NEXT: vins.f16 s2, s6 762; CHECK-MVE-NEXT: vmovx.f16 s6, s3 763; CHECK-MVE-NEXT: vcmp.f16 s6, s4 764; CHECK-MVE-NEXT: vmovx.f16 s6, s11 765; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 766; CHECK-MVE-NEXT: vcmp.f16 s3, s4 767; CHECK-MVE-NEXT: cset r0, gt 768; CHECK-MVE-NEXT: cmp r0, #0 769; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 770; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 771; CHECK-MVE-NEXT: cset r0, gt 772; CHECK-MVE-NEXT: cmp r0, #0 773; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 774; CHECK-MVE-NEXT: vins.f16 s3, s6 775; CHECK-MVE-NEXT: bx lr 776; 777; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: 778; CHECK-MVEFP: @ %bb.0: @ %entry 779; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 780; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 781; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 782; CHECK-MVEFP-NEXT: bx lr 783entry: 784 %i = insertelement <8 x half> undef, half %src2, i32 0 785 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 786 %c = fcmp ogt <8 x half> %src, %sp 787 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 788 ret <8 x half> %s 789} 790 791define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 792; CHECK-MVE-LABEL: vcmp_oge_v8f16: 793; CHECK-MVE: @ %bb.0: @ %entry 794; CHECK-MVE-NEXT: vmovx.f16 s6, s0 795; CHECK-MVE-NEXT: vmovx.f16 s5, s12 796; CHECK-MVE-NEXT: vcmp.f16 s6, s4 797; CHECK-MVE-NEXT: vmovx.f16 s6, s8 798; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 799; CHECK-MVE-NEXT: vcmp.f16 s0, s4 800; CHECK-MVE-NEXT: cset r0, ge 801; CHECK-MVE-NEXT: cmp r0, #0 802; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 803; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 804; CHECK-MVE-NEXT: cset r0, ge 805; CHECK-MVE-NEXT: cmp r0, #0 806; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 807; CHECK-MVE-NEXT: vmovx.f16 s8, s13 808; CHECK-MVE-NEXT: vins.f16 s0, s6 809; CHECK-MVE-NEXT: vmovx.f16 s6, s1 810; CHECK-MVE-NEXT: vcmp.f16 s6, s4 811; CHECK-MVE-NEXT: vmovx.f16 s6, s9 812; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 813; CHECK-MVE-NEXT: vcmp.f16 s1, s4 814; CHECK-MVE-NEXT: cset r0, ge 815; CHECK-MVE-NEXT: cmp r0, #0 816; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 817; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 818; CHECK-MVE-NEXT: vmovx.f16 s8, s14 819; CHECK-MVE-NEXT: cset r0, ge 820; CHECK-MVE-NEXT: cmp r0, #0 821; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 822; CHECK-MVE-NEXT: vins.f16 s1, s6 823; CHECK-MVE-NEXT: vmovx.f16 s6, s2 824; CHECK-MVE-NEXT: vcmp.f16 s6, s4 825; CHECK-MVE-NEXT: vmovx.f16 s6, s10 826; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 827; CHECK-MVE-NEXT: vcmp.f16 s2, s4 828; CHECK-MVE-NEXT: cset r0, ge 829; CHECK-MVE-NEXT: cmp r0, #0 830; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 831; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 832; CHECK-MVE-NEXT: vmovx.f16 s8, s15 833; CHECK-MVE-NEXT: cset r0, ge 834; CHECK-MVE-NEXT: cmp r0, #0 835; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 836; CHECK-MVE-NEXT: vins.f16 s2, s6 837; CHECK-MVE-NEXT: vmovx.f16 s6, s3 838; CHECK-MVE-NEXT: vcmp.f16 s6, s4 839; CHECK-MVE-NEXT: vmovx.f16 s6, s11 840; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 841; CHECK-MVE-NEXT: vcmp.f16 s3, s4 842; CHECK-MVE-NEXT: cset r0, ge 843; CHECK-MVE-NEXT: cmp r0, #0 844; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 845; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 846; CHECK-MVE-NEXT: cset r0, ge 847; CHECK-MVE-NEXT: cmp r0, #0 848; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 849; CHECK-MVE-NEXT: vins.f16 s3, s6 850; CHECK-MVE-NEXT: bx lr 851; 852; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: 853; CHECK-MVEFP: @ %bb.0: @ %entry 854; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 855; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 856; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 857; CHECK-MVEFP-NEXT: bx lr 858entry: 859 %i = insertelement <8 x half> undef, half %src2, i32 0 860 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 861 %c = fcmp oge <8 x half> %src, %sp 862 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 863 ret <8 x half> %s 864} 865 866define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 867; CHECK-MVE-LABEL: vcmp_olt_v8f16: 868; CHECK-MVE: @ %bb.0: @ %entry 869; CHECK-MVE-NEXT: vmovx.f16 s6, s0 870; CHECK-MVE-NEXT: vmovx.f16 s5, s12 871; CHECK-MVE-NEXT: vcmp.f16 s6, s4 872; CHECK-MVE-NEXT: vmovx.f16 s6, s8 873; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 874; CHECK-MVE-NEXT: vcmp.f16 s0, s4 875; CHECK-MVE-NEXT: cset r0, mi 876; CHECK-MVE-NEXT: cmp r0, #0 877; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 878; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 879; CHECK-MVE-NEXT: cset r0, mi 880; CHECK-MVE-NEXT: cmp r0, #0 881; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 882; CHECK-MVE-NEXT: vmovx.f16 s8, s13 883; CHECK-MVE-NEXT: vins.f16 s0, s6 884; CHECK-MVE-NEXT: vmovx.f16 s6, s1 885; CHECK-MVE-NEXT: vcmp.f16 s6, s4 886; CHECK-MVE-NEXT: vmovx.f16 s6, s9 887; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 888; CHECK-MVE-NEXT: vcmp.f16 s1, s4 889; CHECK-MVE-NEXT: cset r0, mi 890; CHECK-MVE-NEXT: cmp r0, #0 891; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 892; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 893; CHECK-MVE-NEXT: vmovx.f16 s8, s14 894; CHECK-MVE-NEXT: cset r0, mi 895; CHECK-MVE-NEXT: cmp r0, #0 896; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 897; CHECK-MVE-NEXT: vins.f16 s1, s6 898; CHECK-MVE-NEXT: vmovx.f16 s6, s2 899; CHECK-MVE-NEXT: vcmp.f16 s6, s4 900; CHECK-MVE-NEXT: vmovx.f16 s6, s10 901; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 902; CHECK-MVE-NEXT: vcmp.f16 s2, s4 903; CHECK-MVE-NEXT: cset r0, mi 904; CHECK-MVE-NEXT: cmp r0, #0 905; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 906; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 907; CHECK-MVE-NEXT: vmovx.f16 s8, s15 908; CHECK-MVE-NEXT: cset r0, mi 909; CHECK-MVE-NEXT: cmp r0, #0 910; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 911; CHECK-MVE-NEXT: vins.f16 s2, s6 912; CHECK-MVE-NEXT: vmovx.f16 s6, s3 913; CHECK-MVE-NEXT: vcmp.f16 s6, s4 914; CHECK-MVE-NEXT: vmovx.f16 s6, s11 915; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 916; CHECK-MVE-NEXT: vcmp.f16 s3, s4 917; CHECK-MVE-NEXT: cset r0, mi 918; CHECK-MVE-NEXT: cmp r0, #0 919; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 920; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 921; CHECK-MVE-NEXT: cset r0, mi 922; CHECK-MVE-NEXT: cmp r0, #0 923; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 924; CHECK-MVE-NEXT: vins.f16 s3, s6 925; CHECK-MVE-NEXT: bx lr 926; 927; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: 928; CHECK-MVEFP: @ %bb.0: @ %entry 929; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 930; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 931; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 932; CHECK-MVEFP-NEXT: bx lr 933entry: 934 %i = insertelement <8 x half> undef, half %src2, i32 0 935 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 936 %c = fcmp olt <8 x half> %src, %sp 937 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 938 ret <8 x half> %s 939} 940 941define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 942; CHECK-MVE-LABEL: vcmp_ole_v8f16: 943; CHECK-MVE: @ %bb.0: @ %entry 944; CHECK-MVE-NEXT: vmovx.f16 s6, s0 945; CHECK-MVE-NEXT: vmovx.f16 s5, s12 946; CHECK-MVE-NEXT: vcmp.f16 s6, s4 947; CHECK-MVE-NEXT: vmovx.f16 s6, s8 948; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 949; CHECK-MVE-NEXT: vcmp.f16 s0, s4 950; CHECK-MVE-NEXT: cset r0, ls 951; CHECK-MVE-NEXT: cmp r0, #0 952; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 953; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 954; CHECK-MVE-NEXT: cset r0, ls 955; CHECK-MVE-NEXT: cmp r0, #0 956; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 957; CHECK-MVE-NEXT: vmovx.f16 s8, s13 958; CHECK-MVE-NEXT: vins.f16 s0, s6 959; CHECK-MVE-NEXT: vmovx.f16 s6, s1 960; CHECK-MVE-NEXT: vcmp.f16 s6, s4 961; CHECK-MVE-NEXT: vmovx.f16 s6, s9 962; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 963; CHECK-MVE-NEXT: vcmp.f16 s1, s4 964; CHECK-MVE-NEXT: cset r0, ls 965; CHECK-MVE-NEXT: cmp r0, #0 966; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 967; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 968; CHECK-MVE-NEXT: vmovx.f16 s8, s14 969; CHECK-MVE-NEXT: cset r0, ls 970; CHECK-MVE-NEXT: cmp r0, #0 971; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 972; CHECK-MVE-NEXT: vins.f16 s1, s6 973; CHECK-MVE-NEXT: vmovx.f16 s6, s2 974; CHECK-MVE-NEXT: vcmp.f16 s6, s4 975; CHECK-MVE-NEXT: vmovx.f16 s6, s10 976; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 977; CHECK-MVE-NEXT: vcmp.f16 s2, s4 978; CHECK-MVE-NEXT: cset r0, ls 979; CHECK-MVE-NEXT: cmp r0, #0 980; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 981; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 982; CHECK-MVE-NEXT: vmovx.f16 s8, s15 983; CHECK-MVE-NEXT: cset r0, ls 984; CHECK-MVE-NEXT: cmp r0, #0 985; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 986; CHECK-MVE-NEXT: vins.f16 s2, s6 987; CHECK-MVE-NEXT: vmovx.f16 s6, s3 988; CHECK-MVE-NEXT: vcmp.f16 s6, s4 989; CHECK-MVE-NEXT: vmovx.f16 s6, s11 990; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 991; CHECK-MVE-NEXT: vcmp.f16 s3, s4 992; CHECK-MVE-NEXT: cset r0, ls 993; CHECK-MVE-NEXT: cmp r0, #0 994; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 995; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 996; CHECK-MVE-NEXT: cset r0, ls 997; CHECK-MVE-NEXT: cmp r0, #0 998; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 999; CHECK-MVE-NEXT: vins.f16 s3, s6 1000; CHECK-MVE-NEXT: bx lr 1001; 1002; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: 1003; CHECK-MVEFP: @ %bb.0: @ %entry 1004; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1005; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 1006; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1007; CHECK-MVEFP-NEXT: bx lr 1008entry: 1009 %i = insertelement <8 x half> undef, half %src2, i32 0 1010 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1011 %c = fcmp ole <8 x half> %src, %sp 1012 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1013 ret <8 x half> %s 1014} 1015 1016define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 1017; CHECK-MVE-LABEL: vcmp_ueq_v8f16: 1018; CHECK-MVE: @ %bb.0: @ %entry 1019; CHECK-MVE-NEXT: vmovx.f16 s6, s0 1020; CHECK-MVE-NEXT: vmovx.f16 s5, s12 1021; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1022; CHECK-MVE-NEXT: vmovx.f16 s6, s8 1023; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1024; CHECK-MVE-NEXT: vcmp.f16 s0, s4 1025; CHECK-MVE-NEXT: cset r0, eq 1026; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1027; CHECK-MVE-NEXT: cmp r0, #0 1028; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 1029; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1030; CHECK-MVE-NEXT: cset r0, eq 1031; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1032; CHECK-MVE-NEXT: cmp r0, #0 1033; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 1034; CHECK-MVE-NEXT: vmovx.f16 s8, s13 1035; CHECK-MVE-NEXT: vins.f16 s0, s6 1036; CHECK-MVE-NEXT: vmovx.f16 s6, s1 1037; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1038; CHECK-MVE-NEXT: vmovx.f16 s6, s9 1039; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1040; CHECK-MVE-NEXT: vcmp.f16 s1, s4 1041; CHECK-MVE-NEXT: cset r0, eq 1042; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1043; CHECK-MVE-NEXT: cmp r0, #0 1044; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1045; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1046; CHECK-MVE-NEXT: vmovx.f16 s8, s14 1047; CHECK-MVE-NEXT: cset r0, eq 1048; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1049; CHECK-MVE-NEXT: cmp r0, #0 1050; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 1051; CHECK-MVE-NEXT: vins.f16 s1, s6 1052; CHECK-MVE-NEXT: vmovx.f16 s6, s2 1053; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1054; CHECK-MVE-NEXT: vmovx.f16 s6, s10 1055; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1056; CHECK-MVE-NEXT: vcmp.f16 s2, s4 1057; CHECK-MVE-NEXT: cset r0, eq 1058; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1059; CHECK-MVE-NEXT: cmp r0, #0 1060; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1061; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1062; CHECK-MVE-NEXT: vmovx.f16 s8, s15 1063; CHECK-MVE-NEXT: cset r0, eq 1064; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1065; CHECK-MVE-NEXT: cmp r0, #0 1066; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 1067; CHECK-MVE-NEXT: vins.f16 s2, s6 1068; CHECK-MVE-NEXT: vmovx.f16 s6, s3 1069; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1070; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1071; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1072; CHECK-MVE-NEXT: vcmp.f16 s3, s4 1073; CHECK-MVE-NEXT: cset r0, eq 1074; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1075; CHECK-MVE-NEXT: cmp r0, #0 1076; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1077; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1078; CHECK-MVE-NEXT: cset r0, eq 1079; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1080; CHECK-MVE-NEXT: cmp r0, #0 1081; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 1082; CHECK-MVE-NEXT: vins.f16 s3, s6 1083; CHECK-MVE-NEXT: bx lr 1084; 1085; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: 1086; CHECK-MVEFP: @ %bb.0: @ %entry 1087; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1088; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 1089; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0 1090; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1091; CHECK-MVEFP-NEXT: bx lr 1092entry: 1093 %i = insertelement <8 x half> undef, half %src2, i32 0 1094 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1095 %c = fcmp ueq <8 x half> %src, %sp 1096 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1097 ret <8 x half> %s 1098} 1099 1100define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 1101; CHECK-MVE-LABEL: vcmp_une_v8f16: 1102; CHECK-MVE: @ %bb.0: @ %entry 1103; CHECK-MVE-NEXT: vmovx.f16 s6, s0 1104; CHECK-MVE-NEXT: vmovx.f16 s5, s12 1105; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1106; CHECK-MVE-NEXT: vmovx.f16 s6, s8 1107; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1108; CHECK-MVE-NEXT: vcmp.f16 s0, s4 1109; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 1110; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1111; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 1112; CHECK-MVE-NEXT: vmovx.f16 s8, s13 1113; CHECK-MVE-NEXT: vins.f16 s0, s6 1114; CHECK-MVE-NEXT: vmovx.f16 s6, s1 1115; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1116; CHECK-MVE-NEXT: vmovx.f16 s6, s9 1117; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1118; CHECK-MVE-NEXT: vcmp.f16 s1, s4 1119; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1120; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1121; CHECK-MVE-NEXT: vmovx.f16 s8, s14 1122; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 1123; CHECK-MVE-NEXT: vins.f16 s1, s6 1124; CHECK-MVE-NEXT: vmovx.f16 s6, s2 1125; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1126; CHECK-MVE-NEXT: vmovx.f16 s6, s10 1127; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1128; CHECK-MVE-NEXT: vcmp.f16 s2, s4 1129; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1130; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1131; CHECK-MVE-NEXT: vmovx.f16 s8, s15 1132; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 1133; CHECK-MVE-NEXT: vins.f16 s2, s6 1134; CHECK-MVE-NEXT: vmovx.f16 s6, s3 1135; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1136; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1137; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1138; CHECK-MVE-NEXT: vcmp.f16 s3, s4 1139; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1140; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1141; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 1142; CHECK-MVE-NEXT: vins.f16 s3, s6 1143; CHECK-MVE-NEXT: bx lr 1144; 1145; CHECK-MVEFP-LABEL: vcmp_une_v8f16: 1146; CHECK-MVEFP: @ %bb.0: @ %entry 1147; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1148; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 1149; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1150; CHECK-MVEFP-NEXT: bx lr 1151entry: 1152 %i = insertelement <8 x half> undef, half %src2, i32 0 1153 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1154 %c = fcmp une <8 x half> %src, %sp 1155 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1156 ret <8 x half> %s 1157} 1158 1159define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 1160; CHECK-MVE-LABEL: vcmp_ugt_v8f16: 1161; CHECK-MVE: @ %bb.0: @ %entry 1162; CHECK-MVE-NEXT: vmovx.f16 s6, s0 1163; CHECK-MVE-NEXT: vmovx.f16 s5, s12 1164; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1165; CHECK-MVE-NEXT: vmovx.f16 s6, s8 1166; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1167; CHECK-MVE-NEXT: vcmp.f16 s0, s4 1168; CHECK-MVE-NEXT: cset r0, hi 1169; CHECK-MVE-NEXT: cmp r0, #0 1170; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 1171; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1172; CHECK-MVE-NEXT: cset r0, hi 1173; CHECK-MVE-NEXT: cmp r0, #0 1174; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 1175; CHECK-MVE-NEXT: vmovx.f16 s8, s13 1176; CHECK-MVE-NEXT: vins.f16 s0, s6 1177; CHECK-MVE-NEXT: vmovx.f16 s6, s1 1178; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1179; CHECK-MVE-NEXT: vmovx.f16 s6, s9 1180; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1181; CHECK-MVE-NEXT: vcmp.f16 s1, s4 1182; CHECK-MVE-NEXT: cset r0, hi 1183; CHECK-MVE-NEXT: cmp r0, #0 1184; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1185; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1186; CHECK-MVE-NEXT: vmovx.f16 s8, s14 1187; CHECK-MVE-NEXT: cset r0, hi 1188; CHECK-MVE-NEXT: cmp r0, #0 1189; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 1190; CHECK-MVE-NEXT: vins.f16 s1, s6 1191; CHECK-MVE-NEXT: vmovx.f16 s6, s2 1192; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1193; CHECK-MVE-NEXT: vmovx.f16 s6, s10 1194; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1195; CHECK-MVE-NEXT: vcmp.f16 s2, s4 1196; CHECK-MVE-NEXT: cset r0, hi 1197; CHECK-MVE-NEXT: cmp r0, #0 1198; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1199; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1200; CHECK-MVE-NEXT: vmovx.f16 s8, s15 1201; CHECK-MVE-NEXT: cset r0, hi 1202; CHECK-MVE-NEXT: cmp r0, #0 1203; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 1204; CHECK-MVE-NEXT: vins.f16 s2, s6 1205; CHECK-MVE-NEXT: vmovx.f16 s6, s3 1206; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1207; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1208; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1209; CHECK-MVE-NEXT: vcmp.f16 s3, s4 1210; CHECK-MVE-NEXT: cset r0, hi 1211; CHECK-MVE-NEXT: cmp r0, #0 1212; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1213; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1214; CHECK-MVE-NEXT: cset r0, hi 1215; CHECK-MVE-NEXT: cmp r0, #0 1216; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 1217; CHECK-MVE-NEXT: vins.f16 s3, s6 1218; CHECK-MVE-NEXT: bx lr 1219; 1220; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: 1221; CHECK-MVEFP: @ %bb.0: @ %entry 1222; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1223; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 1224; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1225; CHECK-MVEFP-NEXT: bx lr 1226entry: 1227 %i = insertelement <8 x half> undef, half %src2, i32 0 1228 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1229 %c = fcmp ugt <8 x half> %src, %sp 1230 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1231 ret <8 x half> %s 1232} 1233 1234define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 1235; CHECK-MVE-LABEL: vcmp_uge_v8f16: 1236; CHECK-MVE: @ %bb.0: @ %entry 1237; CHECK-MVE-NEXT: vmovx.f16 s6, s0 1238; CHECK-MVE-NEXT: vmovx.f16 s5, s12 1239; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1240; CHECK-MVE-NEXT: vmovx.f16 s6, s8 1241; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1242; CHECK-MVE-NEXT: vcmp.f16 s0, s4 1243; CHECK-MVE-NEXT: cset r0, pl 1244; CHECK-MVE-NEXT: cmp r0, #0 1245; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 1246; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1247; CHECK-MVE-NEXT: cset r0, pl 1248; CHECK-MVE-NEXT: cmp r0, #0 1249; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 1250; CHECK-MVE-NEXT: vmovx.f16 s8, s13 1251; CHECK-MVE-NEXT: vins.f16 s0, s6 1252; CHECK-MVE-NEXT: vmovx.f16 s6, s1 1253; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1254; CHECK-MVE-NEXT: vmovx.f16 s6, s9 1255; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1256; CHECK-MVE-NEXT: vcmp.f16 s1, s4 1257; CHECK-MVE-NEXT: cset r0, pl 1258; CHECK-MVE-NEXT: cmp r0, #0 1259; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1260; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1261; CHECK-MVE-NEXT: vmovx.f16 s8, s14 1262; CHECK-MVE-NEXT: cset r0, pl 1263; CHECK-MVE-NEXT: cmp r0, #0 1264; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 1265; CHECK-MVE-NEXT: vins.f16 s1, s6 1266; CHECK-MVE-NEXT: vmovx.f16 s6, s2 1267; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1268; CHECK-MVE-NEXT: vmovx.f16 s6, s10 1269; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1270; CHECK-MVE-NEXT: vcmp.f16 s2, s4 1271; CHECK-MVE-NEXT: cset r0, pl 1272; CHECK-MVE-NEXT: cmp r0, #0 1273; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1274; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1275; CHECK-MVE-NEXT: vmovx.f16 s8, s15 1276; CHECK-MVE-NEXT: cset r0, pl 1277; CHECK-MVE-NEXT: cmp r0, #0 1278; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 1279; CHECK-MVE-NEXT: vins.f16 s2, s6 1280; CHECK-MVE-NEXT: vmovx.f16 s6, s3 1281; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1282; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1283; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1284; CHECK-MVE-NEXT: vcmp.f16 s3, s4 1285; CHECK-MVE-NEXT: cset r0, pl 1286; CHECK-MVE-NEXT: cmp r0, #0 1287; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1288; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1289; CHECK-MVE-NEXT: cset r0, pl 1290; CHECK-MVE-NEXT: cmp r0, #0 1291; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 1292; CHECK-MVE-NEXT: vins.f16 s3, s6 1293; CHECK-MVE-NEXT: bx lr 1294; 1295; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: 1296; CHECK-MVEFP: @ %bb.0: @ %entry 1297; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1298; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 1299; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1300; CHECK-MVEFP-NEXT: bx lr 1301entry: 1302 %i = insertelement <8 x half> undef, half %src2, i32 0 1303 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1304 %c = fcmp uge <8 x half> %src, %sp 1305 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1306 ret <8 x half> %s 1307} 1308 1309define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 1310; CHECK-MVE-LABEL: vcmp_ult_v8f16: 1311; CHECK-MVE: @ %bb.0: @ %entry 1312; CHECK-MVE-NEXT: vmovx.f16 s6, s0 1313; CHECK-MVE-NEXT: vmovx.f16 s5, s12 1314; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1315; CHECK-MVE-NEXT: vmovx.f16 s6, s8 1316; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1317; CHECK-MVE-NEXT: vcmp.f16 s0, s4 1318; CHECK-MVE-NEXT: cset r0, lt 1319; CHECK-MVE-NEXT: cmp r0, #0 1320; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 1321; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1322; CHECK-MVE-NEXT: cset r0, lt 1323; CHECK-MVE-NEXT: cmp r0, #0 1324; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 1325; CHECK-MVE-NEXT: vmovx.f16 s8, s13 1326; CHECK-MVE-NEXT: vins.f16 s0, s6 1327; CHECK-MVE-NEXT: vmovx.f16 s6, s1 1328; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1329; CHECK-MVE-NEXT: vmovx.f16 s6, s9 1330; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1331; CHECK-MVE-NEXT: vcmp.f16 s1, s4 1332; CHECK-MVE-NEXT: cset r0, lt 1333; CHECK-MVE-NEXT: cmp r0, #0 1334; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1335; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1336; CHECK-MVE-NEXT: vmovx.f16 s8, s14 1337; CHECK-MVE-NEXT: cset r0, lt 1338; CHECK-MVE-NEXT: cmp r0, #0 1339; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 1340; CHECK-MVE-NEXT: vins.f16 s1, s6 1341; CHECK-MVE-NEXT: vmovx.f16 s6, s2 1342; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1343; CHECK-MVE-NEXT: vmovx.f16 s6, s10 1344; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1345; CHECK-MVE-NEXT: vcmp.f16 s2, s4 1346; CHECK-MVE-NEXT: cset r0, lt 1347; CHECK-MVE-NEXT: cmp r0, #0 1348; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1349; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1350; CHECK-MVE-NEXT: vmovx.f16 s8, s15 1351; CHECK-MVE-NEXT: cset r0, lt 1352; CHECK-MVE-NEXT: cmp r0, #0 1353; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 1354; CHECK-MVE-NEXT: vins.f16 s2, s6 1355; CHECK-MVE-NEXT: vmovx.f16 s6, s3 1356; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1357; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1358; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1359; CHECK-MVE-NEXT: vcmp.f16 s3, s4 1360; CHECK-MVE-NEXT: cset r0, lt 1361; CHECK-MVE-NEXT: cmp r0, #0 1362; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1363; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1364; CHECK-MVE-NEXT: cset r0, lt 1365; CHECK-MVE-NEXT: cmp r0, #0 1366; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 1367; CHECK-MVE-NEXT: vins.f16 s3, s6 1368; CHECK-MVE-NEXT: bx lr 1369; 1370; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: 1371; CHECK-MVEFP: @ %bb.0: @ %entry 1372; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1373; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 1374; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1375; CHECK-MVEFP-NEXT: bx lr 1376entry: 1377 %i = insertelement <8 x half> undef, half %src2, i32 0 1378 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1379 %c = fcmp ult <8 x half> %src, %sp 1380 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1381 ret <8 x half> %s 1382} 1383 1384define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 1385; CHECK-MVE-LABEL: vcmp_ule_v8f16: 1386; CHECK-MVE: @ %bb.0: @ %entry 1387; CHECK-MVE-NEXT: vmovx.f16 s6, s0 1388; CHECK-MVE-NEXT: vmovx.f16 s5, s12 1389; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1390; CHECK-MVE-NEXT: vmovx.f16 s6, s8 1391; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1392; CHECK-MVE-NEXT: vcmp.f16 s0, s4 1393; CHECK-MVE-NEXT: cset r0, le 1394; CHECK-MVE-NEXT: cmp r0, #0 1395; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 1396; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1397; CHECK-MVE-NEXT: cset r0, le 1398; CHECK-MVE-NEXT: cmp r0, #0 1399; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 1400; CHECK-MVE-NEXT: vmovx.f16 s8, s13 1401; CHECK-MVE-NEXT: vins.f16 s0, s6 1402; CHECK-MVE-NEXT: vmovx.f16 s6, s1 1403; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1404; CHECK-MVE-NEXT: vmovx.f16 s6, s9 1405; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1406; CHECK-MVE-NEXT: vcmp.f16 s1, s4 1407; CHECK-MVE-NEXT: cset r0, le 1408; CHECK-MVE-NEXT: cmp r0, #0 1409; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1410; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1411; CHECK-MVE-NEXT: vmovx.f16 s8, s14 1412; CHECK-MVE-NEXT: cset r0, le 1413; CHECK-MVE-NEXT: cmp r0, #0 1414; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 1415; CHECK-MVE-NEXT: vins.f16 s1, s6 1416; CHECK-MVE-NEXT: vmovx.f16 s6, s2 1417; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1418; CHECK-MVE-NEXT: vmovx.f16 s6, s10 1419; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1420; CHECK-MVE-NEXT: vcmp.f16 s2, s4 1421; CHECK-MVE-NEXT: cset r0, le 1422; CHECK-MVE-NEXT: cmp r0, #0 1423; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1424; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1425; CHECK-MVE-NEXT: vmovx.f16 s8, s15 1426; CHECK-MVE-NEXT: cset r0, le 1427; CHECK-MVE-NEXT: cmp r0, #0 1428; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 1429; CHECK-MVE-NEXT: vins.f16 s2, s6 1430; CHECK-MVE-NEXT: vmovx.f16 s6, s3 1431; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1432; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1433; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1434; CHECK-MVE-NEXT: vcmp.f16 s3, s4 1435; CHECK-MVE-NEXT: cset r0, le 1436; CHECK-MVE-NEXT: cmp r0, #0 1437; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1438; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1439; CHECK-MVE-NEXT: cset r0, le 1440; CHECK-MVE-NEXT: cmp r0, #0 1441; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 1442; CHECK-MVE-NEXT: vins.f16 s3, s6 1443; CHECK-MVE-NEXT: bx lr 1444; 1445; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: 1446; CHECK-MVEFP: @ %bb.0: @ %entry 1447; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1448; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 1449; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1450; CHECK-MVEFP-NEXT: bx lr 1451entry: 1452 %i = insertelement <8 x half> undef, half %src2, i32 0 1453 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1454 %c = fcmp ule <8 x half> %src, %sp 1455 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1456 ret <8 x half> %s 1457} 1458 1459define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 1460; CHECK-MVE-LABEL: vcmp_ord_v8f16: 1461; CHECK-MVE: @ %bb.0: @ %entry 1462; CHECK-MVE-NEXT: vmovx.f16 s6, s0 1463; CHECK-MVE-NEXT: vmovx.f16 s5, s12 1464; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1465; CHECK-MVE-NEXT: vmovx.f16 s6, s8 1466; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1467; CHECK-MVE-NEXT: vcmp.f16 s0, s4 1468; CHECK-MVE-NEXT: cset r0, vc 1469; CHECK-MVE-NEXT: cmp r0, #0 1470; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 1471; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1472; CHECK-MVE-NEXT: cset r0, vc 1473; CHECK-MVE-NEXT: cmp r0, #0 1474; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 1475; CHECK-MVE-NEXT: vmovx.f16 s8, s13 1476; CHECK-MVE-NEXT: vins.f16 s0, s6 1477; CHECK-MVE-NEXT: vmovx.f16 s6, s1 1478; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1479; CHECK-MVE-NEXT: vmovx.f16 s6, s9 1480; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1481; CHECK-MVE-NEXT: vcmp.f16 s1, s4 1482; CHECK-MVE-NEXT: cset r0, vc 1483; CHECK-MVE-NEXT: cmp r0, #0 1484; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1485; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1486; CHECK-MVE-NEXT: vmovx.f16 s8, s14 1487; CHECK-MVE-NEXT: cset r0, vc 1488; CHECK-MVE-NEXT: cmp r0, #0 1489; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 1490; CHECK-MVE-NEXT: vins.f16 s1, s6 1491; CHECK-MVE-NEXT: vmovx.f16 s6, s2 1492; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1493; CHECK-MVE-NEXT: vmovx.f16 s6, s10 1494; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1495; CHECK-MVE-NEXT: vcmp.f16 s2, s4 1496; CHECK-MVE-NEXT: cset r0, vc 1497; CHECK-MVE-NEXT: cmp r0, #0 1498; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1499; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1500; CHECK-MVE-NEXT: vmovx.f16 s8, s15 1501; CHECK-MVE-NEXT: cset r0, vc 1502; CHECK-MVE-NEXT: cmp r0, #0 1503; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 1504; CHECK-MVE-NEXT: vins.f16 s2, s6 1505; CHECK-MVE-NEXT: vmovx.f16 s6, s3 1506; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1507; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1508; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1509; CHECK-MVE-NEXT: vcmp.f16 s3, s4 1510; CHECK-MVE-NEXT: cset r0, vc 1511; CHECK-MVE-NEXT: cmp r0, #0 1512; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1513; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1514; CHECK-MVE-NEXT: cset r0, vc 1515; CHECK-MVE-NEXT: cmp r0, #0 1516; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 1517; CHECK-MVE-NEXT: vins.f16 s3, s6 1518; CHECK-MVE-NEXT: bx lr 1519; 1520; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: 1521; CHECK-MVEFP: @ %bb.0: @ %entry 1522; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1523; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 1524; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0 1525; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 1526; CHECK-MVEFP-NEXT: bx lr 1527entry: 1528 %i = insertelement <8 x half> undef, half %src2, i32 0 1529 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1530 %c = fcmp ord <8 x half> %src, %sp 1531 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1532 ret <8 x half> %s 1533} 1534 1535define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 1536; CHECK-MVE-LABEL: vcmp_uno_v8f16: 1537; CHECK-MVE: @ %bb.0: @ %entry 1538; CHECK-MVE-NEXT: vmovx.f16 s6, s0 1539; CHECK-MVE-NEXT: vmovx.f16 s5, s12 1540; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1541; CHECK-MVE-NEXT: vmovx.f16 s6, s8 1542; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1543; CHECK-MVE-NEXT: vcmp.f16 s0, s4 1544; CHECK-MVE-NEXT: cset r0, vs 1545; CHECK-MVE-NEXT: cmp r0, #0 1546; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 1547; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1548; CHECK-MVE-NEXT: cset r0, vs 1549; CHECK-MVE-NEXT: cmp r0, #0 1550; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 1551; CHECK-MVE-NEXT: vmovx.f16 s8, s13 1552; CHECK-MVE-NEXT: vins.f16 s0, s6 1553; CHECK-MVE-NEXT: vmovx.f16 s6, s1 1554; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1555; CHECK-MVE-NEXT: vmovx.f16 s6, s9 1556; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1557; CHECK-MVE-NEXT: vcmp.f16 s1, s4 1558; CHECK-MVE-NEXT: cset r0, vs 1559; CHECK-MVE-NEXT: cmp r0, #0 1560; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1561; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1562; CHECK-MVE-NEXT: vmovx.f16 s8, s14 1563; CHECK-MVE-NEXT: cset r0, vs 1564; CHECK-MVE-NEXT: cmp r0, #0 1565; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 1566; CHECK-MVE-NEXT: vins.f16 s1, s6 1567; CHECK-MVE-NEXT: vmovx.f16 s6, s2 1568; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1569; CHECK-MVE-NEXT: vmovx.f16 s6, s10 1570; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1571; CHECK-MVE-NEXT: vcmp.f16 s2, s4 1572; CHECK-MVE-NEXT: cset r0, vs 1573; CHECK-MVE-NEXT: cmp r0, #0 1574; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1575; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1576; CHECK-MVE-NEXT: vmovx.f16 s8, s15 1577; CHECK-MVE-NEXT: cset r0, vs 1578; CHECK-MVE-NEXT: cmp r0, #0 1579; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 1580; CHECK-MVE-NEXT: vins.f16 s2, s6 1581; CHECK-MVE-NEXT: vmovx.f16 s6, s3 1582; CHECK-MVE-NEXT: vcmp.f16 s6, s4 1583; CHECK-MVE-NEXT: vmovx.f16 s6, s11 1584; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1585; CHECK-MVE-NEXT: vcmp.f16 s3, s4 1586; CHECK-MVE-NEXT: cset r0, vs 1587; CHECK-MVE-NEXT: cmp r0, #0 1588; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 1589; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1590; CHECK-MVE-NEXT: cset r0, vs 1591; CHECK-MVE-NEXT: cmp r0, #0 1592; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 1593; CHECK-MVE-NEXT: vins.f16 s3, s6 1594; CHECK-MVE-NEXT: bx lr 1595; 1596; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: 1597; CHECK-MVEFP: @ %bb.0: @ %entry 1598; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 1599; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 1600; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0 1601; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1602; CHECK-MVEFP-NEXT: bx lr 1603entry: 1604 %i = insertelement <8 x half> undef, half %src2, i32 0 1605 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 1606 %c = fcmp uno <8 x half> %src, %sp 1607 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 1608 ret <8 x half> %s 1609} 1610 1611 1612; Reversed 1613 1614define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1615; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32: 1616; CHECK-MVE: @ %bb.0: @ %entry 1617; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1618; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1619; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1620; CHECK-MVE-NEXT: cset r0, eq 1621; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1622; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1623; CHECK-MVE-NEXT: cset r1, eq 1624; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1625; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1626; CHECK-MVE-NEXT: cset r2, eq 1627; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1628; CHECK-MVE-NEXT: cset r3, eq 1629; CHECK-MVE-NEXT: cmp r3, #0 1630; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1631; CHECK-MVE-NEXT: cmp r2, #0 1632; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1633; CHECK-MVE-NEXT: cmp r1, #0 1634; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1635; CHECK-MVE-NEXT: cmp r0, #0 1636; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1637; CHECK-MVE-NEXT: bx lr 1638; 1639; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32: 1640; CHECK-MVEFP: @ %bb.0: @ %entry 1641; CHECK-MVEFP-NEXT: vmov r0, s4 1642; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, r0 1643; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1644; CHECK-MVEFP-NEXT: bx lr 1645entry: 1646 %i = insertelement <4 x float> undef, float %src2, i32 0 1647 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1648 %c = fcmp oeq <4 x float> %sp, %src 1649 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1650 ret <4 x float> %s 1651} 1652 1653define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1654; CHECK-MVE-LABEL: vcmp_r_one_v4f32: 1655; CHECK-MVE: @ %bb.0: @ %entry 1656; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1657; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1658; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1659; CHECK-MVE-NEXT: cset r0, mi 1660; CHECK-MVE-NEXT: csinc r0, r0, zr, le 1661; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1662; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1663; CHECK-MVE-NEXT: cset r1, mi 1664; CHECK-MVE-NEXT: csinc r1, r1, zr, le 1665; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1666; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1667; CHECK-MVE-NEXT: cset r2, mi 1668; CHECK-MVE-NEXT: csinc r2, r2, zr, le 1669; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1670; CHECK-MVE-NEXT: cset r3, mi 1671; CHECK-MVE-NEXT: csinc r3, r3, zr, le 1672; CHECK-MVE-NEXT: cmp r3, #0 1673; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1674; CHECK-MVE-NEXT: cmp r2, #0 1675; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1676; CHECK-MVE-NEXT: cmp r1, #0 1677; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1678; CHECK-MVE-NEXT: cmp r0, #0 1679; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1680; CHECK-MVE-NEXT: bx lr 1681; 1682; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32: 1683; CHECK-MVEFP: @ %bb.0: @ %entry 1684; CHECK-MVEFP-NEXT: vmov r0, s4 1685; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 1686; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0 1687; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 1688; CHECK-MVEFP-NEXT: bx lr 1689entry: 1690 %i = insertelement <4 x float> undef, float %src2, i32 0 1691 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1692 %c = fcmp one <4 x float> %sp, %src 1693 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1694 ret <4 x float> %s 1695} 1696 1697define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1698; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32: 1699; CHECK-MVE: @ %bb.0: @ %entry 1700; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1701; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1702; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1703; CHECK-MVE-NEXT: cset r0, gt 1704; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1705; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1706; CHECK-MVE-NEXT: cset r1, gt 1707; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1708; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1709; CHECK-MVE-NEXT: cset r2, gt 1710; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1711; CHECK-MVE-NEXT: cset r3, gt 1712; CHECK-MVE-NEXT: cmp r3, #0 1713; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1714; CHECK-MVE-NEXT: cmp r2, #0 1715; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1716; CHECK-MVE-NEXT: cmp r1, #0 1717; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1718; CHECK-MVE-NEXT: cmp r0, #0 1719; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1720; CHECK-MVE-NEXT: bx lr 1721; 1722; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32: 1723; CHECK-MVEFP: @ %bb.0: @ %entry 1724; CHECK-MVEFP-NEXT: vmov r0, s4 1725; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 1726; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1727; CHECK-MVEFP-NEXT: bx lr 1728entry: 1729 %i = insertelement <4 x float> undef, float %src2, i32 0 1730 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1731 %c = fcmp ogt <4 x float> %sp, %src 1732 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1733 ret <4 x float> %s 1734} 1735 1736define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1737; CHECK-MVE-LABEL: vcmp_r_oge_v4f32: 1738; CHECK-MVE: @ %bb.0: @ %entry 1739; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1740; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1741; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1742; CHECK-MVE-NEXT: cset r0, ge 1743; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1744; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1745; CHECK-MVE-NEXT: cset r1, ge 1746; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1747; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1748; CHECK-MVE-NEXT: cset r2, ge 1749; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1750; CHECK-MVE-NEXT: cset r3, ge 1751; CHECK-MVE-NEXT: cmp r3, #0 1752; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1753; CHECK-MVE-NEXT: cmp r2, #0 1754; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1755; CHECK-MVE-NEXT: cmp r1, #0 1756; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1757; CHECK-MVE-NEXT: cmp r0, #0 1758; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1759; CHECK-MVE-NEXT: bx lr 1760; 1761; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32: 1762; CHECK-MVEFP: @ %bb.0: @ %entry 1763; CHECK-MVEFP-NEXT: vmov r0, s4 1764; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 1765; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1766; CHECK-MVEFP-NEXT: bx lr 1767entry: 1768 %i = insertelement <4 x float> undef, float %src2, i32 0 1769 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1770 %c = fcmp oge <4 x float> %sp, %src 1771 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1772 ret <4 x float> %s 1773} 1774 1775define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1776; CHECK-MVE-LABEL: vcmp_r_olt_v4f32: 1777; CHECK-MVE: @ %bb.0: @ %entry 1778; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1779; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1780; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1781; CHECK-MVE-NEXT: cset r0, mi 1782; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1783; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1784; CHECK-MVE-NEXT: cset r1, mi 1785; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1786; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1787; CHECK-MVE-NEXT: cset r2, mi 1788; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1789; CHECK-MVE-NEXT: cset r3, mi 1790; CHECK-MVE-NEXT: cmp r3, #0 1791; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1792; CHECK-MVE-NEXT: cmp r2, #0 1793; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1794; CHECK-MVE-NEXT: cmp r1, #0 1795; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1796; CHECK-MVE-NEXT: cmp r0, #0 1797; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1798; CHECK-MVE-NEXT: bx lr 1799; 1800; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32: 1801; CHECK-MVEFP: @ %bb.0: @ %entry 1802; CHECK-MVEFP-NEXT: vmov r0, s4 1803; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 1804; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1805; CHECK-MVEFP-NEXT: bx lr 1806entry: 1807 %i = insertelement <4 x float> undef, float %src2, i32 0 1808 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1809 %c = fcmp olt <4 x float> %sp, %src 1810 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1811 ret <4 x float> %s 1812} 1813 1814define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1815; CHECK-MVE-LABEL: vcmp_r_ole_v4f32: 1816; CHECK-MVE: @ %bb.0: @ %entry 1817; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1818; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1819; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1820; CHECK-MVE-NEXT: cset r0, ls 1821; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1822; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1823; CHECK-MVE-NEXT: cset r1, ls 1824; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1825; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1826; CHECK-MVE-NEXT: cset r2, ls 1827; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1828; CHECK-MVE-NEXT: cset r3, ls 1829; CHECK-MVE-NEXT: cmp r3, #0 1830; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1831; CHECK-MVE-NEXT: cmp r2, #0 1832; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1833; CHECK-MVE-NEXT: cmp r1, #0 1834; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1835; CHECK-MVE-NEXT: cmp r0, #0 1836; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1837; CHECK-MVE-NEXT: bx lr 1838; 1839; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32: 1840; CHECK-MVEFP: @ %bb.0: @ %entry 1841; CHECK-MVEFP-NEXT: vmov r0, s4 1842; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 1843; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1844; CHECK-MVEFP-NEXT: bx lr 1845entry: 1846 %i = insertelement <4 x float> undef, float %src2, i32 0 1847 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1848 %c = fcmp ole <4 x float> %sp, %src 1849 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1850 ret <4 x float> %s 1851} 1852 1853define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1854; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32: 1855; CHECK-MVE: @ %bb.0: @ %entry 1856; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1857; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1858; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1859; CHECK-MVE-NEXT: cset r0, eq 1860; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 1861; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1862; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1863; CHECK-MVE-NEXT: cset r1, eq 1864; CHECK-MVE-NEXT: csinc r1, r1, zr, vc 1865; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1866; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1867; CHECK-MVE-NEXT: cset r2, eq 1868; CHECK-MVE-NEXT: csinc r2, r2, zr, vc 1869; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1870; CHECK-MVE-NEXT: cset r3, eq 1871; CHECK-MVE-NEXT: csinc r3, r3, zr, vc 1872; CHECK-MVE-NEXT: cmp r3, #0 1873; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1874; CHECK-MVE-NEXT: cmp r2, #0 1875; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1876; CHECK-MVE-NEXT: cmp r1, #0 1877; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1878; CHECK-MVE-NEXT: cmp r0, #0 1879; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1880; CHECK-MVE-NEXT: bx lr 1881; 1882; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32: 1883; CHECK-MVEFP: @ %bb.0: @ %entry 1884; CHECK-MVEFP-NEXT: vmov r0, s4 1885; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 1886; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0 1887; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1888; CHECK-MVEFP-NEXT: bx lr 1889entry: 1890 %i = insertelement <4 x float> undef, float %src2, i32 0 1891 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1892 %c = fcmp ueq <4 x float> %sp, %src 1893 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1894 ret <4 x float> %s 1895} 1896 1897define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1898; CHECK-MVE-LABEL: vcmp_r_une_v4f32: 1899; CHECK-MVE: @ %bb.0: @ %entry 1900; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1901; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1902; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1903; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1904; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1905; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1906; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1907; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1908; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1909; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1910; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1911; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1912; CHECK-MVE-NEXT: bx lr 1913; 1914; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32: 1915; CHECK-MVEFP: @ %bb.0: @ %entry 1916; CHECK-MVEFP-NEXT: vmov r0, s4 1917; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, r0 1918; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1919; CHECK-MVEFP-NEXT: bx lr 1920entry: 1921 %i = insertelement <4 x float> undef, float %src2, i32 0 1922 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1923 %c = fcmp une <4 x float> %sp, %src 1924 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1925 ret <4 x float> %s 1926} 1927 1928define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1929; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32: 1930; CHECK-MVE: @ %bb.0: @ %entry 1931; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1932; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1933; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1934; CHECK-MVE-NEXT: cset r0, hi 1935; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1936; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1937; CHECK-MVE-NEXT: cset r1, hi 1938; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1939; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1940; CHECK-MVE-NEXT: cset r2, hi 1941; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1942; CHECK-MVE-NEXT: cset r3, hi 1943; CHECK-MVE-NEXT: cmp r3, #0 1944; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1945; CHECK-MVE-NEXT: cmp r2, #0 1946; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1947; CHECK-MVE-NEXT: cmp r1, #0 1948; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1949; CHECK-MVE-NEXT: cmp r0, #0 1950; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1951; CHECK-MVE-NEXT: bx lr 1952; 1953; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32: 1954; CHECK-MVEFP: @ %bb.0: @ %entry 1955; CHECK-MVEFP-NEXT: vmov r0, s4 1956; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 1957; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1958; CHECK-MVEFP-NEXT: bx lr 1959entry: 1960 %i = insertelement <4 x float> undef, float %src2, i32 0 1961 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 1962 %c = fcmp ugt <4 x float> %sp, %src 1963 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 1964 ret <4 x float> %s 1965} 1966 1967define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 1968; CHECK-MVE-LABEL: vcmp_r_uge_v4f32: 1969; CHECK-MVE: @ %bb.0: @ %entry 1970; CHECK-MVE-NEXT: vcmp.f32 s4, s0 1971; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1972; CHECK-MVE-NEXT: vcmp.f32 s4, s3 1973; CHECK-MVE-NEXT: cset r0, pl 1974; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1975; CHECK-MVE-NEXT: vcmp.f32 s4, s1 1976; CHECK-MVE-NEXT: cset r1, pl 1977; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1978; CHECK-MVE-NEXT: vcmp.f32 s4, s2 1979; CHECK-MVE-NEXT: cset r2, pl 1980; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 1981; CHECK-MVE-NEXT: cset r3, pl 1982; CHECK-MVE-NEXT: cmp r3, #0 1983; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 1984; CHECK-MVE-NEXT: cmp r2, #0 1985; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 1986; CHECK-MVE-NEXT: cmp r1, #0 1987; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 1988; CHECK-MVE-NEXT: cmp r0, #0 1989; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 1990; CHECK-MVE-NEXT: bx lr 1991; 1992; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32: 1993; CHECK-MVEFP: @ %bb.0: @ %entry 1994; CHECK-MVEFP-NEXT: vmov r0, s4 1995; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 1996; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 1997; CHECK-MVEFP-NEXT: bx lr 1998entry: 1999 %i = insertelement <4 x float> undef, float %src2, i32 0 2000 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 2001 %c = fcmp uge <4 x float> %sp, %src 2002 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 2003 ret <4 x float> %s 2004} 2005 2006define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 2007; CHECK-MVE-LABEL: vcmp_r_ult_v4f32: 2008; CHECK-MVE: @ %bb.0: @ %entry 2009; CHECK-MVE-NEXT: vcmp.f32 s4, s0 2010; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2011; CHECK-MVE-NEXT: vcmp.f32 s4, s3 2012; CHECK-MVE-NEXT: cset r0, lt 2013; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2014; CHECK-MVE-NEXT: vcmp.f32 s4, s1 2015; CHECK-MVE-NEXT: cset r1, lt 2016; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2017; CHECK-MVE-NEXT: vcmp.f32 s4, s2 2018; CHECK-MVE-NEXT: cset r2, lt 2019; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2020; CHECK-MVE-NEXT: cset r3, lt 2021; CHECK-MVE-NEXT: cmp r3, #0 2022; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 2023; CHECK-MVE-NEXT: cmp r2, #0 2024; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 2025; CHECK-MVE-NEXT: cmp r1, #0 2026; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 2027; CHECK-MVE-NEXT: cmp r0, #0 2028; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 2029; CHECK-MVE-NEXT: bx lr 2030; 2031; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32: 2032; CHECK-MVEFP: @ %bb.0: @ %entry 2033; CHECK-MVEFP-NEXT: vmov r0, s4 2034; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 2035; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2036; CHECK-MVEFP-NEXT: bx lr 2037entry: 2038 %i = insertelement <4 x float> undef, float %src2, i32 0 2039 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 2040 %c = fcmp ult <4 x float> %sp, %src 2041 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 2042 ret <4 x float> %s 2043} 2044 2045define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 2046; CHECK-MVE-LABEL: vcmp_r_ule_v4f32: 2047; CHECK-MVE: @ %bb.0: @ %entry 2048; CHECK-MVE-NEXT: vcmp.f32 s4, s0 2049; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2050; CHECK-MVE-NEXT: vcmp.f32 s4, s3 2051; CHECK-MVE-NEXT: cset r0, le 2052; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2053; CHECK-MVE-NEXT: vcmp.f32 s4, s1 2054; CHECK-MVE-NEXT: cset r1, le 2055; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2056; CHECK-MVE-NEXT: vcmp.f32 s4, s2 2057; CHECK-MVE-NEXT: cset r2, le 2058; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2059; CHECK-MVE-NEXT: cset r3, le 2060; CHECK-MVE-NEXT: cmp r3, #0 2061; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 2062; CHECK-MVE-NEXT: cmp r2, #0 2063; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 2064; CHECK-MVE-NEXT: cmp r1, #0 2065; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 2066; CHECK-MVE-NEXT: cmp r0, #0 2067; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 2068; CHECK-MVE-NEXT: bx lr 2069; 2070; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32: 2071; CHECK-MVEFP: @ %bb.0: @ %entry 2072; CHECK-MVEFP-NEXT: vmov r0, s4 2073; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 2074; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2075; CHECK-MVEFP-NEXT: bx lr 2076entry: 2077 %i = insertelement <4 x float> undef, float %src2, i32 0 2078 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 2079 %c = fcmp ule <4 x float> %sp, %src 2080 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 2081 ret <4 x float> %s 2082} 2083 2084define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 2085; CHECK-MVE-LABEL: vcmp_r_ord_v4f32: 2086; CHECK-MVE: @ %bb.0: @ %entry 2087; CHECK-MVE-NEXT: vcmp.f32 s4, s0 2088; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2089; CHECK-MVE-NEXT: vcmp.f32 s4, s3 2090; CHECK-MVE-NEXT: cset r0, vc 2091; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2092; CHECK-MVE-NEXT: vcmp.f32 s4, s1 2093; CHECK-MVE-NEXT: cset r1, vc 2094; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2095; CHECK-MVE-NEXT: vcmp.f32 s4, s2 2096; CHECK-MVE-NEXT: cset r2, vc 2097; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2098; CHECK-MVE-NEXT: cset r3, vc 2099; CHECK-MVE-NEXT: cmp r3, #0 2100; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 2101; CHECK-MVE-NEXT: cmp r2, #0 2102; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 2103; CHECK-MVE-NEXT: cmp r1, #0 2104; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 2105; CHECK-MVE-NEXT: cmp r0, #0 2106; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 2107; CHECK-MVE-NEXT: bx lr 2108; 2109; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32: 2110; CHECK-MVEFP: @ %bb.0: @ %entry 2111; CHECK-MVEFP-NEXT: vmov r0, s4 2112; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 2113; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0 2114; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 2115; CHECK-MVEFP-NEXT: bx lr 2116entry: 2117 %i = insertelement <4 x float> undef, float %src2, i32 0 2118 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 2119 %c = fcmp ord <4 x float> %sp, %src 2120 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 2121 ret <4 x float> %s 2122} 2123 2124define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { 2125; CHECK-MVE-LABEL: vcmp_r_uno_v4f32: 2126; CHECK-MVE: @ %bb.0: @ %entry 2127; CHECK-MVE-NEXT: vcmp.f32 s4, s0 2128; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2129; CHECK-MVE-NEXT: vcmp.f32 s4, s3 2130; CHECK-MVE-NEXT: cset r0, vs 2131; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2132; CHECK-MVE-NEXT: vcmp.f32 s4, s1 2133; CHECK-MVE-NEXT: cset r1, vs 2134; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2135; CHECK-MVE-NEXT: vcmp.f32 s4, s2 2136; CHECK-MVE-NEXT: cset r2, vs 2137; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2138; CHECK-MVE-NEXT: cset r3, vs 2139; CHECK-MVE-NEXT: cmp r3, #0 2140; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 2141; CHECK-MVE-NEXT: cmp r2, #0 2142; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 2143; CHECK-MVE-NEXT: cmp r1, #0 2144; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 2145; CHECK-MVE-NEXT: cmp r0, #0 2146; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 2147; CHECK-MVE-NEXT: bx lr 2148; 2149; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32: 2150; CHECK-MVEFP: @ %bb.0: @ %entry 2151; CHECK-MVEFP-NEXT: vmov r0, s4 2152; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 2153; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0 2154; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2155; CHECK-MVEFP-NEXT: bx lr 2156entry: 2157 %i = insertelement <4 x float> undef, float %src2, i32 0 2158 %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer 2159 %c = fcmp uno <4 x float> %sp, %src 2160 %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b 2161 ret <4 x float> %s 2162} 2163 2164 2165 2166define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2167; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16: 2168; CHECK-MVE: @ %bb.0: @ %entry 2169; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2170; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2171; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2172; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2173; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2174; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2175; CHECK-MVE-NEXT: cset r0, eq 2176; CHECK-MVE-NEXT: cmp r0, #0 2177; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2178; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2179; CHECK-MVE-NEXT: cset r0, eq 2180; CHECK-MVE-NEXT: cmp r0, #0 2181; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2182; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2183; CHECK-MVE-NEXT: vins.f16 s0, s6 2184; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2185; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2186; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2187; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2188; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2189; CHECK-MVE-NEXT: cset r0, eq 2190; CHECK-MVE-NEXT: cmp r0, #0 2191; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2192; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2193; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2194; CHECK-MVE-NEXT: cset r0, eq 2195; CHECK-MVE-NEXT: cmp r0, #0 2196; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2197; CHECK-MVE-NEXT: vins.f16 s1, s6 2198; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2199; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2200; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2201; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2202; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2203; CHECK-MVE-NEXT: cset r0, eq 2204; CHECK-MVE-NEXT: cmp r0, #0 2205; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2206; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2207; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2208; CHECK-MVE-NEXT: cset r0, eq 2209; CHECK-MVE-NEXT: cmp r0, #0 2210; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2211; CHECK-MVE-NEXT: vins.f16 s2, s6 2212; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2213; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2214; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2215; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2216; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2217; CHECK-MVE-NEXT: cset r0, eq 2218; CHECK-MVE-NEXT: cmp r0, #0 2219; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2220; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2221; CHECK-MVE-NEXT: cset r0, eq 2222; CHECK-MVE-NEXT: cmp r0, #0 2223; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2224; CHECK-MVE-NEXT: vins.f16 s3, s6 2225; CHECK-MVE-NEXT: bx lr 2226; 2227; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: 2228; CHECK-MVEFP: @ %bb.0: @ %entry 2229; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2230; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 2231; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2232; CHECK-MVEFP-NEXT: bx lr 2233entry: 2234 %i = insertelement <8 x half> undef, half %src2, i32 0 2235 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2236 %c = fcmp oeq <8 x half> %sp, %src 2237 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2238 ret <8 x half> %s 2239} 2240 2241define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2242; CHECK-MVE-LABEL: vcmp_r_one_v8f16: 2243; CHECK-MVE: @ %bb.0: @ %entry 2244; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2245; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2246; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2247; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2248; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2249; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2250; CHECK-MVE-NEXT: cset r0, mi 2251; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2252; CHECK-MVE-NEXT: cmp r0, #0 2253; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2254; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2255; CHECK-MVE-NEXT: cset r0, mi 2256; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2257; CHECK-MVE-NEXT: cmp r0, #0 2258; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2259; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2260; CHECK-MVE-NEXT: vins.f16 s0, s6 2261; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2262; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2263; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2264; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2265; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2266; CHECK-MVE-NEXT: cset r0, mi 2267; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2268; CHECK-MVE-NEXT: cmp r0, #0 2269; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2270; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2271; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2272; CHECK-MVE-NEXT: cset r0, mi 2273; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2274; CHECK-MVE-NEXT: cmp r0, #0 2275; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2276; CHECK-MVE-NEXT: vins.f16 s1, s6 2277; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2278; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2279; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2280; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2281; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2282; CHECK-MVE-NEXT: cset r0, mi 2283; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2284; CHECK-MVE-NEXT: cmp r0, #0 2285; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2286; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2287; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2288; CHECK-MVE-NEXT: cset r0, mi 2289; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2290; CHECK-MVE-NEXT: cmp r0, #0 2291; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2292; CHECK-MVE-NEXT: vins.f16 s2, s6 2293; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2294; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2295; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2296; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2297; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2298; CHECK-MVE-NEXT: cset r0, mi 2299; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2300; CHECK-MVE-NEXT: cmp r0, #0 2301; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2302; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2303; CHECK-MVE-NEXT: cset r0, mi 2304; CHECK-MVE-NEXT: csinc r0, r0, zr, le 2305; CHECK-MVE-NEXT: cmp r0, #0 2306; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2307; CHECK-MVE-NEXT: vins.f16 s3, s6 2308; CHECK-MVE-NEXT: bx lr 2309; 2310; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: 2311; CHECK-MVEFP: @ %bb.0: @ %entry 2312; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2313; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 2314; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0 2315; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 2316; CHECK-MVEFP-NEXT: bx lr 2317entry: 2318 %i = insertelement <8 x half> undef, half %src2, i32 0 2319 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2320 %c = fcmp one <8 x half> %sp, %src 2321 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2322 ret <8 x half> %s 2323} 2324 2325define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2326; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16: 2327; CHECK-MVE: @ %bb.0: @ %entry 2328; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2329; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2330; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2331; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2332; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2333; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2334; CHECK-MVE-NEXT: cset r0, gt 2335; CHECK-MVE-NEXT: cmp r0, #0 2336; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2337; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2338; CHECK-MVE-NEXT: cset r0, gt 2339; CHECK-MVE-NEXT: cmp r0, #0 2340; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2341; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2342; CHECK-MVE-NEXT: vins.f16 s0, s6 2343; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2344; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2345; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2346; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2347; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2348; CHECK-MVE-NEXT: cset r0, gt 2349; CHECK-MVE-NEXT: cmp r0, #0 2350; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2351; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2352; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2353; CHECK-MVE-NEXT: cset r0, gt 2354; CHECK-MVE-NEXT: cmp r0, #0 2355; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2356; CHECK-MVE-NEXT: vins.f16 s1, s6 2357; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2358; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2359; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2360; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2361; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2362; CHECK-MVE-NEXT: cset r0, gt 2363; CHECK-MVE-NEXT: cmp r0, #0 2364; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2365; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2366; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2367; CHECK-MVE-NEXT: cset r0, gt 2368; CHECK-MVE-NEXT: cmp r0, #0 2369; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2370; CHECK-MVE-NEXT: vins.f16 s2, s6 2371; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2372; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2373; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2374; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2375; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2376; CHECK-MVE-NEXT: cset r0, gt 2377; CHECK-MVE-NEXT: cmp r0, #0 2378; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2379; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2380; CHECK-MVE-NEXT: cset r0, gt 2381; CHECK-MVE-NEXT: cmp r0, #0 2382; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2383; CHECK-MVE-NEXT: vins.f16 s3, s6 2384; CHECK-MVE-NEXT: bx lr 2385; 2386; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: 2387; CHECK-MVEFP: @ %bb.0: @ %entry 2388; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2389; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 2390; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2391; CHECK-MVEFP-NEXT: bx lr 2392entry: 2393 %i = insertelement <8 x half> undef, half %src2, i32 0 2394 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2395 %c = fcmp ogt <8 x half> %sp, %src 2396 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2397 ret <8 x half> %s 2398} 2399 2400define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2401; CHECK-MVE-LABEL: vcmp_r_oge_v8f16: 2402; CHECK-MVE: @ %bb.0: @ %entry 2403; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2404; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2405; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2406; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2407; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2408; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2409; CHECK-MVE-NEXT: cset r0, ge 2410; CHECK-MVE-NEXT: cmp r0, #0 2411; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2412; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2413; CHECK-MVE-NEXT: cset r0, ge 2414; CHECK-MVE-NEXT: cmp r0, #0 2415; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2416; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2417; CHECK-MVE-NEXT: vins.f16 s0, s6 2418; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2419; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2420; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2421; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2422; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2423; CHECK-MVE-NEXT: cset r0, ge 2424; CHECK-MVE-NEXT: cmp r0, #0 2425; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2426; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2427; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2428; CHECK-MVE-NEXT: cset r0, ge 2429; CHECK-MVE-NEXT: cmp r0, #0 2430; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2431; CHECK-MVE-NEXT: vins.f16 s1, s6 2432; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2433; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2434; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2435; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2436; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2437; CHECK-MVE-NEXT: cset r0, ge 2438; CHECK-MVE-NEXT: cmp r0, #0 2439; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2440; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2441; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2442; CHECK-MVE-NEXT: cset r0, ge 2443; CHECK-MVE-NEXT: cmp r0, #0 2444; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2445; CHECK-MVE-NEXT: vins.f16 s2, s6 2446; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2447; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2448; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2449; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2450; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2451; CHECK-MVE-NEXT: cset r0, ge 2452; CHECK-MVE-NEXT: cmp r0, #0 2453; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2454; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2455; CHECK-MVE-NEXT: cset r0, ge 2456; CHECK-MVE-NEXT: cmp r0, #0 2457; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2458; CHECK-MVE-NEXT: vins.f16 s3, s6 2459; CHECK-MVE-NEXT: bx lr 2460; 2461; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: 2462; CHECK-MVEFP: @ %bb.0: @ %entry 2463; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2464; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 2465; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2466; CHECK-MVEFP-NEXT: bx lr 2467entry: 2468 %i = insertelement <8 x half> undef, half %src2, i32 0 2469 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2470 %c = fcmp oge <8 x half> %sp, %src 2471 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2472 ret <8 x half> %s 2473} 2474 2475define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2476; CHECK-MVE-LABEL: vcmp_r_olt_v8f16: 2477; CHECK-MVE: @ %bb.0: @ %entry 2478; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2479; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2480; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2481; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2482; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2483; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2484; CHECK-MVE-NEXT: cset r0, mi 2485; CHECK-MVE-NEXT: cmp r0, #0 2486; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2487; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2488; CHECK-MVE-NEXT: cset r0, mi 2489; CHECK-MVE-NEXT: cmp r0, #0 2490; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2491; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2492; CHECK-MVE-NEXT: vins.f16 s0, s6 2493; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2494; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2495; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2496; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2497; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2498; CHECK-MVE-NEXT: cset r0, mi 2499; CHECK-MVE-NEXT: cmp r0, #0 2500; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2501; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2502; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2503; CHECK-MVE-NEXT: cset r0, mi 2504; CHECK-MVE-NEXT: cmp r0, #0 2505; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2506; CHECK-MVE-NEXT: vins.f16 s1, s6 2507; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2508; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2509; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2510; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2511; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2512; CHECK-MVE-NEXT: cset r0, mi 2513; CHECK-MVE-NEXT: cmp r0, #0 2514; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2515; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2516; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2517; CHECK-MVE-NEXT: cset r0, mi 2518; CHECK-MVE-NEXT: cmp r0, #0 2519; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2520; CHECK-MVE-NEXT: vins.f16 s2, s6 2521; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2522; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2523; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2524; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2525; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2526; CHECK-MVE-NEXT: cset r0, mi 2527; CHECK-MVE-NEXT: cmp r0, #0 2528; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2529; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2530; CHECK-MVE-NEXT: cset r0, mi 2531; CHECK-MVE-NEXT: cmp r0, #0 2532; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2533; CHECK-MVE-NEXT: vins.f16 s3, s6 2534; CHECK-MVE-NEXT: bx lr 2535; 2536; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: 2537; CHECK-MVEFP: @ %bb.0: @ %entry 2538; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2539; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 2540; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2541; CHECK-MVEFP-NEXT: bx lr 2542entry: 2543 %i = insertelement <8 x half> undef, half %src2, i32 0 2544 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2545 %c = fcmp olt <8 x half> %sp, %src 2546 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2547 ret <8 x half> %s 2548} 2549 2550define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2551; CHECK-MVE-LABEL: vcmp_r_ole_v8f16: 2552; CHECK-MVE: @ %bb.0: @ %entry 2553; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2554; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2555; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2556; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2557; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2558; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2559; CHECK-MVE-NEXT: cset r0, ls 2560; CHECK-MVE-NEXT: cmp r0, #0 2561; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2562; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2563; CHECK-MVE-NEXT: cset r0, ls 2564; CHECK-MVE-NEXT: cmp r0, #0 2565; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2566; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2567; CHECK-MVE-NEXT: vins.f16 s0, s6 2568; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2569; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2570; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2571; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2572; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2573; CHECK-MVE-NEXT: cset r0, ls 2574; CHECK-MVE-NEXT: cmp r0, #0 2575; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2576; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2577; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2578; CHECK-MVE-NEXT: cset r0, ls 2579; CHECK-MVE-NEXT: cmp r0, #0 2580; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2581; CHECK-MVE-NEXT: vins.f16 s1, s6 2582; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2583; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2584; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2585; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2586; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2587; CHECK-MVE-NEXT: cset r0, ls 2588; CHECK-MVE-NEXT: cmp r0, #0 2589; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2590; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2591; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2592; CHECK-MVE-NEXT: cset r0, ls 2593; CHECK-MVE-NEXT: cmp r0, #0 2594; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2595; CHECK-MVE-NEXT: vins.f16 s2, s6 2596; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2597; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2598; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2599; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2600; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2601; CHECK-MVE-NEXT: cset r0, ls 2602; CHECK-MVE-NEXT: cmp r0, #0 2603; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2604; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2605; CHECK-MVE-NEXT: cset r0, ls 2606; CHECK-MVE-NEXT: cmp r0, #0 2607; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2608; CHECK-MVE-NEXT: vins.f16 s3, s6 2609; CHECK-MVE-NEXT: bx lr 2610; 2611; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: 2612; CHECK-MVEFP: @ %bb.0: @ %entry 2613; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2614; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 2615; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2616; CHECK-MVEFP-NEXT: bx lr 2617entry: 2618 %i = insertelement <8 x half> undef, half %src2, i32 0 2619 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2620 %c = fcmp ole <8 x half> %sp, %src 2621 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2622 ret <8 x half> %s 2623} 2624 2625define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2626; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16: 2627; CHECK-MVE: @ %bb.0: @ %entry 2628; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2629; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2630; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2631; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2632; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2633; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2634; CHECK-MVE-NEXT: cset r0, eq 2635; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2636; CHECK-MVE-NEXT: cmp r0, #0 2637; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2638; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2639; CHECK-MVE-NEXT: cset r0, eq 2640; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2641; CHECK-MVE-NEXT: cmp r0, #0 2642; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2643; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2644; CHECK-MVE-NEXT: vins.f16 s0, s6 2645; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2646; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2647; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2648; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2649; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2650; CHECK-MVE-NEXT: cset r0, eq 2651; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2652; CHECK-MVE-NEXT: cmp r0, #0 2653; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2654; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2655; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2656; CHECK-MVE-NEXT: cset r0, eq 2657; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2658; CHECK-MVE-NEXT: cmp r0, #0 2659; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2660; CHECK-MVE-NEXT: vins.f16 s1, s6 2661; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2662; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2663; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2664; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2665; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2666; CHECK-MVE-NEXT: cset r0, eq 2667; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2668; CHECK-MVE-NEXT: cmp r0, #0 2669; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2670; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2671; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2672; CHECK-MVE-NEXT: cset r0, eq 2673; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2674; CHECK-MVE-NEXT: cmp r0, #0 2675; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2676; CHECK-MVE-NEXT: vins.f16 s2, s6 2677; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2678; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2679; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2680; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2681; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2682; CHECK-MVE-NEXT: cset r0, eq 2683; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2684; CHECK-MVE-NEXT: cmp r0, #0 2685; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2686; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2687; CHECK-MVE-NEXT: cset r0, eq 2688; CHECK-MVE-NEXT: csinc r0, r0, zr, vc 2689; CHECK-MVE-NEXT: cmp r0, #0 2690; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2691; CHECK-MVE-NEXT: vins.f16 s3, s6 2692; CHECK-MVE-NEXT: bx lr 2693; 2694; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: 2695; CHECK-MVEFP: @ %bb.0: @ %entry 2696; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2697; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 2698; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0 2699; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2700; CHECK-MVEFP-NEXT: bx lr 2701entry: 2702 %i = insertelement <8 x half> undef, half %src2, i32 0 2703 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2704 %c = fcmp ueq <8 x half> %sp, %src 2705 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2706 ret <8 x half> %s 2707} 2708 2709define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2710; CHECK-MVE-LABEL: vcmp_r_une_v8f16: 2711; CHECK-MVE: @ %bb.0: @ %entry 2712; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2713; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2714; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2715; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2716; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2717; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2718; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2719; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2720; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2721; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2722; CHECK-MVE-NEXT: vins.f16 s0, s6 2723; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2724; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2725; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2726; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2727; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2728; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2729; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2730; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2731; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2732; CHECK-MVE-NEXT: vins.f16 s1, s6 2733; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2734; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2735; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2736; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2737; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2738; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2739; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2740; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2741; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2742; CHECK-MVE-NEXT: vins.f16 s2, s6 2743; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2744; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2745; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2746; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2747; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2748; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2749; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2750; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2751; CHECK-MVE-NEXT: vins.f16 s3, s6 2752; CHECK-MVE-NEXT: bx lr 2753; 2754; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: 2755; CHECK-MVEFP: @ %bb.0: @ %entry 2756; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2757; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 2758; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2759; CHECK-MVEFP-NEXT: bx lr 2760entry: 2761 %i = insertelement <8 x half> undef, half %src2, i32 0 2762 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2763 %c = fcmp une <8 x half> %sp, %src 2764 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2765 ret <8 x half> %s 2766} 2767 2768define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2769; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16: 2770; CHECK-MVE: @ %bb.0: @ %entry 2771; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2772; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2773; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2774; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2775; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2776; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2777; CHECK-MVE-NEXT: cset r0, hi 2778; CHECK-MVE-NEXT: cmp r0, #0 2779; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2780; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2781; CHECK-MVE-NEXT: cset r0, hi 2782; CHECK-MVE-NEXT: cmp r0, #0 2783; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2784; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2785; CHECK-MVE-NEXT: vins.f16 s0, s6 2786; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2787; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2788; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2789; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2790; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2791; CHECK-MVE-NEXT: cset r0, hi 2792; CHECK-MVE-NEXT: cmp r0, #0 2793; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2794; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2795; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2796; CHECK-MVE-NEXT: cset r0, hi 2797; CHECK-MVE-NEXT: cmp r0, #0 2798; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2799; CHECK-MVE-NEXT: vins.f16 s1, s6 2800; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2801; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2802; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2803; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2804; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2805; CHECK-MVE-NEXT: cset r0, hi 2806; CHECK-MVE-NEXT: cmp r0, #0 2807; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2808; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2809; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2810; CHECK-MVE-NEXT: cset r0, hi 2811; CHECK-MVE-NEXT: cmp r0, #0 2812; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2813; CHECK-MVE-NEXT: vins.f16 s2, s6 2814; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2815; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2816; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2817; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2818; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2819; CHECK-MVE-NEXT: cset r0, hi 2820; CHECK-MVE-NEXT: cmp r0, #0 2821; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2822; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2823; CHECK-MVE-NEXT: cset r0, hi 2824; CHECK-MVE-NEXT: cmp r0, #0 2825; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2826; CHECK-MVE-NEXT: vins.f16 s3, s6 2827; CHECK-MVE-NEXT: bx lr 2828; 2829; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: 2830; CHECK-MVEFP: @ %bb.0: @ %entry 2831; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2832; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 2833; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2834; CHECK-MVEFP-NEXT: bx lr 2835entry: 2836 %i = insertelement <8 x half> undef, half %src2, i32 0 2837 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2838 %c = fcmp ugt <8 x half> %sp, %src 2839 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2840 ret <8 x half> %s 2841} 2842 2843define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2844; CHECK-MVE-LABEL: vcmp_r_uge_v8f16: 2845; CHECK-MVE: @ %bb.0: @ %entry 2846; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2847; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2848; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2849; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2850; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2851; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2852; CHECK-MVE-NEXT: cset r0, pl 2853; CHECK-MVE-NEXT: cmp r0, #0 2854; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2855; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2856; CHECK-MVE-NEXT: cset r0, pl 2857; CHECK-MVE-NEXT: cmp r0, #0 2858; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2859; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2860; CHECK-MVE-NEXT: vins.f16 s0, s6 2861; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2862; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2863; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2864; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2865; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2866; CHECK-MVE-NEXT: cset r0, pl 2867; CHECK-MVE-NEXT: cmp r0, #0 2868; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2869; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2870; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2871; CHECK-MVE-NEXT: cset r0, pl 2872; CHECK-MVE-NEXT: cmp r0, #0 2873; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2874; CHECK-MVE-NEXT: vins.f16 s1, s6 2875; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2876; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2877; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2878; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2879; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2880; CHECK-MVE-NEXT: cset r0, pl 2881; CHECK-MVE-NEXT: cmp r0, #0 2882; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2883; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2884; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2885; CHECK-MVE-NEXT: cset r0, pl 2886; CHECK-MVE-NEXT: cmp r0, #0 2887; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2888; CHECK-MVE-NEXT: vins.f16 s2, s6 2889; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2890; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2891; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2892; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2893; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2894; CHECK-MVE-NEXT: cset r0, pl 2895; CHECK-MVE-NEXT: cmp r0, #0 2896; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2897; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2898; CHECK-MVE-NEXT: cset r0, pl 2899; CHECK-MVE-NEXT: cmp r0, #0 2900; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2901; CHECK-MVE-NEXT: vins.f16 s3, s6 2902; CHECK-MVE-NEXT: bx lr 2903; 2904; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: 2905; CHECK-MVEFP: @ %bb.0: @ %entry 2906; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2907; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 2908; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2909; CHECK-MVEFP-NEXT: bx lr 2910entry: 2911 %i = insertelement <8 x half> undef, half %src2, i32 0 2912 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2913 %c = fcmp uge <8 x half> %sp, %src 2914 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2915 ret <8 x half> %s 2916} 2917 2918define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2919; CHECK-MVE-LABEL: vcmp_r_ult_v8f16: 2920; CHECK-MVE: @ %bb.0: @ %entry 2921; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2922; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2923; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2924; CHECK-MVE-NEXT: vmovx.f16 s6, s8 2925; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2926; CHECK-MVE-NEXT: vcmp.f16 s4, s0 2927; CHECK-MVE-NEXT: cset r0, lt 2928; CHECK-MVE-NEXT: cmp r0, #0 2929; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 2930; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2931; CHECK-MVE-NEXT: cset r0, lt 2932; CHECK-MVE-NEXT: cmp r0, #0 2933; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 2934; CHECK-MVE-NEXT: vmovx.f16 s8, s13 2935; CHECK-MVE-NEXT: vins.f16 s0, s6 2936; CHECK-MVE-NEXT: vmovx.f16 s6, s1 2937; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2938; CHECK-MVE-NEXT: vmovx.f16 s6, s9 2939; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2940; CHECK-MVE-NEXT: vcmp.f16 s4, s1 2941; CHECK-MVE-NEXT: cset r0, lt 2942; CHECK-MVE-NEXT: cmp r0, #0 2943; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2944; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2945; CHECK-MVE-NEXT: vmovx.f16 s8, s14 2946; CHECK-MVE-NEXT: cset r0, lt 2947; CHECK-MVE-NEXT: cmp r0, #0 2948; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 2949; CHECK-MVE-NEXT: vins.f16 s1, s6 2950; CHECK-MVE-NEXT: vmovx.f16 s6, s2 2951; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2952; CHECK-MVE-NEXT: vmovx.f16 s6, s10 2953; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2954; CHECK-MVE-NEXT: vcmp.f16 s4, s2 2955; CHECK-MVE-NEXT: cset r0, lt 2956; CHECK-MVE-NEXT: cmp r0, #0 2957; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2958; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2959; CHECK-MVE-NEXT: vmovx.f16 s8, s15 2960; CHECK-MVE-NEXT: cset r0, lt 2961; CHECK-MVE-NEXT: cmp r0, #0 2962; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 2963; CHECK-MVE-NEXT: vins.f16 s2, s6 2964; CHECK-MVE-NEXT: vmovx.f16 s6, s3 2965; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2966; CHECK-MVE-NEXT: vmovx.f16 s6, s11 2967; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2968; CHECK-MVE-NEXT: vcmp.f16 s4, s3 2969; CHECK-MVE-NEXT: cset r0, lt 2970; CHECK-MVE-NEXT: cmp r0, #0 2971; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 2972; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 2973; CHECK-MVE-NEXT: cset r0, lt 2974; CHECK-MVE-NEXT: cmp r0, #0 2975; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 2976; CHECK-MVE-NEXT: vins.f16 s3, s6 2977; CHECK-MVE-NEXT: bx lr 2978; 2979; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: 2980; CHECK-MVEFP: @ %bb.0: @ %entry 2981; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 2982; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 2983; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 2984; CHECK-MVEFP-NEXT: bx lr 2985entry: 2986 %i = insertelement <8 x half> undef, half %src2, i32 0 2987 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 2988 %c = fcmp ult <8 x half> %sp, %src 2989 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 2990 ret <8 x half> %s 2991} 2992 2993define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 2994; CHECK-MVE-LABEL: vcmp_r_ule_v8f16: 2995; CHECK-MVE: @ %bb.0: @ %entry 2996; CHECK-MVE-NEXT: vmovx.f16 s6, s0 2997; CHECK-MVE-NEXT: vmovx.f16 s5, s12 2998; CHECK-MVE-NEXT: vcmp.f16 s4, s6 2999; CHECK-MVE-NEXT: vmovx.f16 s6, s8 3000; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3001; CHECK-MVE-NEXT: vcmp.f16 s4, s0 3002; CHECK-MVE-NEXT: cset r0, le 3003; CHECK-MVE-NEXT: cmp r0, #0 3004; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 3005; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3006; CHECK-MVE-NEXT: cset r0, le 3007; CHECK-MVE-NEXT: cmp r0, #0 3008; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 3009; CHECK-MVE-NEXT: vmovx.f16 s8, s13 3010; CHECK-MVE-NEXT: vins.f16 s0, s6 3011; CHECK-MVE-NEXT: vmovx.f16 s6, s1 3012; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3013; CHECK-MVE-NEXT: vmovx.f16 s6, s9 3014; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3015; CHECK-MVE-NEXT: vcmp.f16 s4, s1 3016; CHECK-MVE-NEXT: cset r0, le 3017; CHECK-MVE-NEXT: cmp r0, #0 3018; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3019; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3020; CHECK-MVE-NEXT: vmovx.f16 s8, s14 3021; CHECK-MVE-NEXT: cset r0, le 3022; CHECK-MVE-NEXT: cmp r0, #0 3023; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 3024; CHECK-MVE-NEXT: vins.f16 s1, s6 3025; CHECK-MVE-NEXT: vmovx.f16 s6, s2 3026; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3027; CHECK-MVE-NEXT: vmovx.f16 s6, s10 3028; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3029; CHECK-MVE-NEXT: vcmp.f16 s4, s2 3030; CHECK-MVE-NEXT: cset r0, le 3031; CHECK-MVE-NEXT: cmp r0, #0 3032; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3033; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3034; CHECK-MVE-NEXT: vmovx.f16 s8, s15 3035; CHECK-MVE-NEXT: cset r0, le 3036; CHECK-MVE-NEXT: cmp r0, #0 3037; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 3038; CHECK-MVE-NEXT: vins.f16 s2, s6 3039; CHECK-MVE-NEXT: vmovx.f16 s6, s3 3040; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3041; CHECK-MVE-NEXT: vmovx.f16 s6, s11 3042; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3043; CHECK-MVE-NEXT: vcmp.f16 s4, s3 3044; CHECK-MVE-NEXT: cset r0, le 3045; CHECK-MVE-NEXT: cmp r0, #0 3046; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3047; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3048; CHECK-MVE-NEXT: cset r0, le 3049; CHECK-MVE-NEXT: cmp r0, #0 3050; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 3051; CHECK-MVE-NEXT: vins.f16 s3, s6 3052; CHECK-MVE-NEXT: bx lr 3053; 3054; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: 3055; CHECK-MVEFP: @ %bb.0: @ %entry 3056; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 3057; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 3058; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 3059; CHECK-MVEFP-NEXT: bx lr 3060entry: 3061 %i = insertelement <8 x half> undef, half %src2, i32 0 3062 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 3063 %c = fcmp ule <8 x half> %sp, %src 3064 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 3065 ret <8 x half> %s 3066} 3067 3068define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 3069; CHECK-MVE-LABEL: vcmp_r_ord_v8f16: 3070; CHECK-MVE: @ %bb.0: @ %entry 3071; CHECK-MVE-NEXT: vmovx.f16 s6, s0 3072; CHECK-MVE-NEXT: vmovx.f16 s5, s12 3073; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3074; CHECK-MVE-NEXT: vmovx.f16 s6, s8 3075; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3076; CHECK-MVE-NEXT: vcmp.f16 s4, s0 3077; CHECK-MVE-NEXT: cset r0, vc 3078; CHECK-MVE-NEXT: cmp r0, #0 3079; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 3080; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3081; CHECK-MVE-NEXT: cset r0, vc 3082; CHECK-MVE-NEXT: cmp r0, #0 3083; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 3084; CHECK-MVE-NEXT: vmovx.f16 s8, s13 3085; CHECK-MVE-NEXT: vins.f16 s0, s6 3086; CHECK-MVE-NEXT: vmovx.f16 s6, s1 3087; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3088; CHECK-MVE-NEXT: vmovx.f16 s6, s9 3089; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3090; CHECK-MVE-NEXT: vcmp.f16 s4, s1 3091; CHECK-MVE-NEXT: cset r0, vc 3092; CHECK-MVE-NEXT: cmp r0, #0 3093; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3094; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3095; CHECK-MVE-NEXT: vmovx.f16 s8, s14 3096; CHECK-MVE-NEXT: cset r0, vc 3097; CHECK-MVE-NEXT: cmp r0, #0 3098; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 3099; CHECK-MVE-NEXT: vins.f16 s1, s6 3100; CHECK-MVE-NEXT: vmovx.f16 s6, s2 3101; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3102; CHECK-MVE-NEXT: vmovx.f16 s6, s10 3103; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3104; CHECK-MVE-NEXT: vcmp.f16 s4, s2 3105; CHECK-MVE-NEXT: cset r0, vc 3106; CHECK-MVE-NEXT: cmp r0, #0 3107; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3108; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3109; CHECK-MVE-NEXT: vmovx.f16 s8, s15 3110; CHECK-MVE-NEXT: cset r0, vc 3111; CHECK-MVE-NEXT: cmp r0, #0 3112; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 3113; CHECK-MVE-NEXT: vins.f16 s2, s6 3114; CHECK-MVE-NEXT: vmovx.f16 s6, s3 3115; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3116; CHECK-MVE-NEXT: vmovx.f16 s6, s11 3117; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3118; CHECK-MVE-NEXT: vcmp.f16 s4, s3 3119; CHECK-MVE-NEXT: cset r0, vc 3120; CHECK-MVE-NEXT: cmp r0, #0 3121; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3122; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3123; CHECK-MVE-NEXT: cset r0, vc 3124; CHECK-MVE-NEXT: cmp r0, #0 3125; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 3126; CHECK-MVE-NEXT: vins.f16 s3, s6 3127; CHECK-MVE-NEXT: bx lr 3128; 3129; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: 3130; CHECK-MVEFP: @ %bb.0: @ %entry 3131; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 3132; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 3133; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0 3134; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 3135; CHECK-MVEFP-NEXT: bx lr 3136entry: 3137 %i = insertelement <8 x half> undef, half %src2, i32 0 3138 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 3139 %c = fcmp ord <8 x half> %sp, %src 3140 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 3141 ret <8 x half> %s 3142} 3143 3144define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 3145; CHECK-MVE-LABEL: vcmp_r_uno_v8f16: 3146; CHECK-MVE: @ %bb.0: @ %entry 3147; CHECK-MVE-NEXT: vmovx.f16 s6, s0 3148; CHECK-MVE-NEXT: vmovx.f16 s5, s12 3149; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3150; CHECK-MVE-NEXT: vmovx.f16 s6, s8 3151; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3152; CHECK-MVE-NEXT: vcmp.f16 s4, s0 3153; CHECK-MVE-NEXT: cset r0, vs 3154; CHECK-MVE-NEXT: cmp r0, #0 3155; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 3156; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3157; CHECK-MVE-NEXT: cset r0, vs 3158; CHECK-MVE-NEXT: cmp r0, #0 3159; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 3160; CHECK-MVE-NEXT: vmovx.f16 s8, s13 3161; CHECK-MVE-NEXT: vins.f16 s0, s6 3162; CHECK-MVE-NEXT: vmovx.f16 s6, s1 3163; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3164; CHECK-MVE-NEXT: vmovx.f16 s6, s9 3165; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3166; CHECK-MVE-NEXT: vcmp.f16 s4, s1 3167; CHECK-MVE-NEXT: cset r0, vs 3168; CHECK-MVE-NEXT: cmp r0, #0 3169; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3170; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3171; CHECK-MVE-NEXT: vmovx.f16 s8, s14 3172; CHECK-MVE-NEXT: cset r0, vs 3173; CHECK-MVE-NEXT: cmp r0, #0 3174; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 3175; CHECK-MVE-NEXT: vins.f16 s1, s6 3176; CHECK-MVE-NEXT: vmovx.f16 s6, s2 3177; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3178; CHECK-MVE-NEXT: vmovx.f16 s6, s10 3179; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3180; CHECK-MVE-NEXT: vcmp.f16 s4, s2 3181; CHECK-MVE-NEXT: cset r0, vs 3182; CHECK-MVE-NEXT: cmp r0, #0 3183; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3184; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3185; CHECK-MVE-NEXT: vmovx.f16 s8, s15 3186; CHECK-MVE-NEXT: cset r0, vs 3187; CHECK-MVE-NEXT: cmp r0, #0 3188; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 3189; CHECK-MVE-NEXT: vins.f16 s2, s6 3190; CHECK-MVE-NEXT: vmovx.f16 s6, s3 3191; CHECK-MVE-NEXT: vcmp.f16 s4, s6 3192; CHECK-MVE-NEXT: vmovx.f16 s6, s11 3193; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3194; CHECK-MVE-NEXT: vcmp.f16 s4, s3 3195; CHECK-MVE-NEXT: cset r0, vs 3196; CHECK-MVE-NEXT: cmp r0, #0 3197; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3198; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3199; CHECK-MVE-NEXT: cset r0, vs 3200; CHECK-MVE-NEXT: cmp r0, #0 3201; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 3202; CHECK-MVE-NEXT: vins.f16 s3, s6 3203; CHECK-MVE-NEXT: bx lr 3204; 3205; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: 3206; CHECK-MVEFP: @ %bb.0: @ %entry 3207; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 3208; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 3209; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0 3210; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 3211; CHECK-MVEFP-NEXT: bx lr 3212entry: 3213 %i = insertelement <8 x half> undef, half %src2, i32 0 3214 %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer 3215 %c = fcmp uno <8 x half> %sp, %src 3216 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 3217 ret <8 x half> %s 3218} 3219 3220 3221 3222define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { 3223; CHECK-MVE-LABEL: vcmp_oeq_v8f16_bc: 3224; CHECK-MVE: @ %bb.0: @ %entry 3225; CHECK-MVE-NEXT: vmovx.f16 s6, s0 3226; CHECK-MVE-NEXT: vmovx.f16 s5, s12 3227; CHECK-MVE-NEXT: vcmp.f16 s6, s4 3228; CHECK-MVE-NEXT: vmovx.f16 s6, s8 3229; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3230; CHECK-MVE-NEXT: vcmp.f16 s0, s4 3231; CHECK-MVE-NEXT: cset r0, eq 3232; CHECK-MVE-NEXT: cmp r0, #0 3233; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 3234; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3235; CHECK-MVE-NEXT: cset r0, eq 3236; CHECK-MVE-NEXT: cmp r0, #0 3237; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 3238; CHECK-MVE-NEXT: vmovx.f16 s8, s13 3239; CHECK-MVE-NEXT: vins.f16 s0, s6 3240; CHECK-MVE-NEXT: vmovx.f16 s6, s1 3241; CHECK-MVE-NEXT: vcmp.f16 s6, s4 3242; CHECK-MVE-NEXT: vmovx.f16 s6, s9 3243; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3244; CHECK-MVE-NEXT: vcmp.f16 s1, s4 3245; CHECK-MVE-NEXT: cset r0, eq 3246; CHECK-MVE-NEXT: cmp r0, #0 3247; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3248; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3249; CHECK-MVE-NEXT: vmovx.f16 s8, s14 3250; CHECK-MVE-NEXT: cset r0, eq 3251; CHECK-MVE-NEXT: cmp r0, #0 3252; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 3253; CHECK-MVE-NEXT: vins.f16 s1, s6 3254; CHECK-MVE-NEXT: vmovx.f16 s6, s2 3255; CHECK-MVE-NEXT: vcmp.f16 s6, s4 3256; CHECK-MVE-NEXT: vmovx.f16 s6, s10 3257; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3258; CHECK-MVE-NEXT: vcmp.f16 s2, s4 3259; CHECK-MVE-NEXT: cset r0, eq 3260; CHECK-MVE-NEXT: cmp r0, #0 3261; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3262; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3263; CHECK-MVE-NEXT: vmovx.f16 s8, s15 3264; CHECK-MVE-NEXT: cset r0, eq 3265; CHECK-MVE-NEXT: cmp r0, #0 3266; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 3267; CHECK-MVE-NEXT: vins.f16 s2, s6 3268; CHECK-MVE-NEXT: vmovx.f16 s6, s3 3269; CHECK-MVE-NEXT: vcmp.f16 s6, s4 3270; CHECK-MVE-NEXT: vmovx.f16 s6, s11 3271; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3272; CHECK-MVE-NEXT: vcmp.f16 s3, s4 3273; CHECK-MVE-NEXT: cset r0, eq 3274; CHECK-MVE-NEXT: cmp r0, #0 3275; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 3276; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr 3277; CHECK-MVE-NEXT: cset r0, eq 3278; CHECK-MVE-NEXT: cmp r0, #0 3279; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 3280; CHECK-MVE-NEXT: vins.f16 s3, s6 3281; CHECK-MVE-NEXT: bx lr 3282; 3283; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16_bc: 3284; CHECK-MVEFP: @ %bb.0: @ %entry 3285; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 3286; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 3287; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 3288; CHECK-MVEFP-NEXT: bx lr 3289entry: 3290 %src2bc = bitcast half %src2 to i16 3291 %i = insertelement <8 x i16> undef, i16 %src2bc, i32 0 3292 %spbc = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 3293 %sp = bitcast <8 x i16> %spbc to <8 x half> 3294 %c = fcmp oeq <8 x half> %src, %sp 3295 %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b 3296 ret <8 x half> %s 3297} 3298