H A D | AArch64ISelLowering.cpp | 1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===// 5 // SPDX-License-Identifier: Apache-2. 3096 changeVectorFPCCToAArch64CC(ISD::CondCode CC,AArch64CC::CondCode & CondCode,AArch64CC::CondCode & CondCode2,bool & Invert) changeVectorFPCCToAArch64CC() argument 3849 valueToCarryFlag(SDValue Value,SelectionDAG & DAG,bool Invert) valueToCarryFlag() argument 3862 carryFlagToValue(SDValue Glue,EVT VT,SelectionDAG & DAG,bool Invert) carryFlagToValue() argument 4033 SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NewVT, MVT::Other}, LowerVectorFP_TO_INT() local 4066 SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {ExtVT, MVT::Other}, LowerVectorFP_TO_INT() local 4071 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0)); LowerVectorFP_TO_INT() local 4105 SDValue Ext = LowerFP_TO_INT() local 5997 SDValue Ext = DAG.getNode(ExtType, DL, MVT::v8i16, BC); LowerLOAD() local 6393 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op.getOperand(0)); LowerOperation() local 6403 SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other}, LowerOperation() local 11372 SDValue Ext = V.getOperand(X * 4 + Y); ReconstructTruncateFromBuildVector() local 11818 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, GeneratePerfectShuffle() local 14908 __anon5c8f63cd1802(Instruction *Ext) areExtractExts() argument 17069 if (SDValue Ext = performMulVectorExtendCombine(N, DAG)) performMulCombine() local 17071 if (SDValue Ext = performMulVectorCmpZeroCombine(N, DAG)) performMulCombine() local 19052 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, DL, ExtVT, VecToExtend); performBuildVectorCombine() local 19519 SDValue Ext = DAG.getNode(Other.getOpcode(), DL, DVT, NewOp); performExtBinopLoadFold() local 19770 SDValue EXT = DAG.getNode(AArch64ISD::EXT, dl, ByteVT, Op0, Op1, Op2); LowerSVEIntrinsicEXT() local 21242 SDValue Ext = Store->getValue(); foldTruncStoreOfExt() local 22626 getTestBitOperand(SDValue Op,unsigned & Bit,bool & Invert,SelectionDAG & DAG) getTestBitOperand() argument 22703 bool Invert = false; performTBZCombine() local 23315 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(), performSignExtendInRegCombine() local [all...] |