Lines Matching +full:invert +full:- +full:ext
1 //=== AArch64PostLegalizerLowering.cpp --------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// Post-legalization lowering for instructions.
20 //===----------------------------------------------------------------------===//
57 #define DEBUG_TYPE "aarch64-postlegalizer-lowering"
71 /// Used for matching target-supported shuffles before codegen.
86 // Look for the first non-undef element.
102 // The index of an EXT is the first element if it is not UNDEF.
103 // Watch out for the beginning UNDEFs. The EXT index should be the expected
105 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
106 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
113 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
114 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
120 Imm -= NumElts;
137 int LastLHSMismatch = -1, LastRHSMismatch = -1;
139 if (M[Idx] == -1) {
147 const int NumNeededToMatch = NumInputElements - 1;
212 /// \param [in] MI - The shuffle vector instruction.
213 /// \param [out] MatchInfo - Either G_UZP1 or G_UZP2 on success.
273 if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(),
278 if (!mi_match(InsMI->getOperand(3).getReg(), MRI, m_ZeroInt()))
282 {InsMI->getOperand(2).getReg()});
297 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg();
320 // Check if an EXT instruction can handle the shuffle mask when the vector
389 /// Special-cased because the constant operand must be emitted as a G_CONSTANT
438 "Expected a power-2 vector size");
439 auto Mask = Builder.buildConstant(IdxTy, VecTy.getNumElements() - 1);
485 SrcLane -= NumElts;
508 /// isVShiftRImm - Check if this is a valid vector for the immediate
547 /// G_ICMP instruction such that the right-hand side is an arithmetic immediate.
567 uint64_t OriginalC = ValAndVReg->Value.getZExtValue();
572 // We have a non-arithmetic immediate. Check if adjusting the immediate and
581 // x slt c => x sle c - 1
582 // x sge c => x sgt c - 1
589 C -= 1;
595 // x ult c => x ule c - 1
596 // x uge c => x ugt c - 1
602 C -= 1;
658 /// \p MI - The G_ICMP instruction
659 /// \p MatchInfo - The new RHS immediate and predicate on success
684 RHS.setReg(Cst->getOperand(0).getReg());
769 Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1);
780 Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1);
795 if (Splat->isReg())
800 int64_t Cst = Splat->getCst();
801 return (Cst != 0 && Cst != -1);
829 uint64_t Mask = ValAndVReg->Value.getZExtValue();
837 unsigned Opc = Def->getOpcode();
843 getIConstantVRegValWithLookThrough(Def->getOperand(2).getReg(), MRI);
846 uint64_t ShiftAmt = MaybeShiftAmt->Value.getZExtValue();
848 getDefIgnoringCopies(Def->getOperand(1).getReg(), MRI);
856 LLT Ty = MRI.getType(Def->getOperand(0).getReg());
883 if (RHSCst && isLegalArithImmed(RHSCst->Value.getSExtValue()))
890 return isCMN(Def, Pred, MRI) ? Def->getOperand(2).getReg() : Reg;
917 /// \param [in] IsZero - True if the comparison is against 0.
918 /// \param [in] NoNans - True if the target has NoNansFPMath.
973 /// Try to lower a vector G_FCMP \p MI into an AArch64-specific pseudo.
977 const auto &ST = MI.getMF()->getSubtarget<AArch64Subtarget>();
993 /// Try to lower a vector G_FCMP \p MI into an AArch64-specific pseudo.
997 const auto &ST = MI.getMF()->getSubtarget<AArch64Subtarget>();
1010 // Compares against 0 have special target-specific pseudos.
1011 bool IsZero = Splat && Splat->isCst() && Splat->getCst() == 0;
1013 bool Invert = false;
1027 changeVectorFCMPPredToAArch64CC(Pred, CC, CC2, Invert);
1033 ST.getTargetLowering()->getTargetMachine().Options.NoNaNsFPMath;
1045 if (Invert)
1105 MachineInstr *Ext = getOpcodeDef(AArch64::G_EXT, Unmerge.getSourceReg(), MRI);
1106 if (!Ext)
1109 Register ExtSrc1 = Ext->getOperand(1).getReg();
1110 Register ExtSrc2 = Ext->getOperand(2).getReg();
1112 getIConstantVRegValWithLookThrough(Ext->getOperand(3).getReg(), MRI);
1113 if (!LowestVal || LowestVal->Value.getZExtValue() != DstTy.getSizeInBytes())
1135 // Match mul({z/s}ext , {z/s}ext) => {u/s}mull OR
1148 unsigned I1Opc = I1->getOpcode();
1149 unsigned I2Opc = I2->getOpcode();
1152 (MRI.getType(I1->getOperand(0).getReg()).getScalarSizeInBits() ==
1153 MRI.getType(I1->getOperand(1).getReg()).getScalarSizeInBits() * 2) &&
1154 (MRI.getType(I2->getOperand(0).getReg()).getScalarSizeInBits() ==
1155 MRI.getType(I2->getOperand(1).getReg()).getScalarSizeInBits() * 2)) {
1177 unsigned I1Opc = I1->getOpcode();
1178 unsigned I2Opc = I2->getOpcode();
1181 (MRI.getType(I1->getOperand(0).getReg()).getScalarSizeInBits() ==
1182 MRI.getType(I1->getOperand(1).getReg()).getScalarSizeInBits() * 2) &&
1183 (MRI.getType(I2->getOperand(0).getReg()).getScalarSizeInBits() ==
1184 MRI.getType(I2->getOperand(1).getReg()).getScalarSizeInBits() * 2)) {
1187 B.buildInstr(I1->getOpcode() == TargetOpcode::G_ZEXT ? AArch64::G_UMULL
1190 {I1->getOperand(1).getReg(), I2->getOperand(1).getReg()});