Lines Matching +full:invert +full:- +full:ext
1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
55 #define DEBUG_TYPE "lanai-lower"
68 "lanai-constant-mul-threshold", cl::Hidden,
152 // statements. Re-evaluate this on new benchmarks.
160 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
162 MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
164 MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
209 //===----------------------------------------------------------------------===//
211 //===----------------------------------------------------------------------===//
280 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
296 if (isInt<16>(C->getSExtValue())) {
297 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
306 if (C->getZExtValue() == 0) {
314 if (isUInt<16>(C->getZExtValue())) {
315 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
323 if (C->getZExtValue() <= 31) {
324 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
332 int64_t Val = C->getSExtValue();
341 int64_t Val = C->getSExtValue();
342 if ((Val >= -33554432) && (Val <= 33554431)) {
360 //===----------------------------------------------------------------------===//
362 //===----------------------------------------------------------------------===//
433 // LowerCCCArguments - transform physical registers into virtual registers and
464 // If this is an 8/16-bit value, it is really passed promoted to 32
465 // bits. Insert an assert[sz]ext to capture this, then truncate to the
511 Register Reg = LanaiMFI->getSRetReturnReg();
514 LanaiMFI->setSRetReturnReg(Reg);
524 LanaiMFI->setVarArgsFrameIndex(FI);
545 // CCValAssign - represent the assignment of the return value to a location
548 // CCState - Info about the registers and stack slot.
577 Register Reg = LanaiMFI->getSRetReturnReg();
600 // LowerCCCCallTo - functions arguments are copied from virtual regs to
617 const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
619 NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
717 // Build a sequence of copy-to-reg nodes chained together with token chain and
728 // Likewise ExternalSymbol -> TargetExternalSymbol.
732 G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
735 E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
744 // Add a register mask operand representing the call-preserved registers.
745 // TODO: Should return-twice functions be handled?
747 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
774 // LowerCallResult - Lower the result values of a call into the
799 //===----------------------------------------------------------------------===//
801 //===----------------------------------------------------------------------===//
805 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
816 if (RHSC->getZExtValue() == 0xFFFFFFFF) {
817 // X > -1 -> X >= 0 -> is_plus(X)
826 if (RHSC->getZExtValue() == 0)
827 // X < 0 -> is_minus(X)
834 if (RHSC->getZExtValue() == 0xFFFFFFFF) {
835 // X <= -1 -> X < 0 -> is_minus(X)
844 if (RHSC->getZExtValue() == 0)
845 // X >= 0 -> is_plus(X)
886 EVT VT = Op->getValueType(0);
890 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
894 int64_t MulAmt = C->getSExtValue();
895 int32_t HighestOne = -1;
899 // Convert to non-adjacent form (NAF) signed-digit representation.
900 // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
902 // digits will be non-zero vs 1/2 for regular binary representation). And as
903 // the non-zero digits will be the only digits contributing to the instruction
906 // choosing the non-zero coefficients such that the resulting quotient is
909 int S = (MulAmt < 0 ? -1 : 1);
914 ZI = 2 - (E % 4);
921 E = (E - ZI) / 2;
927 // Start by assuming a shift and a add/sub for every non-zero entry (hence
928 // every non-zero entry requires 1 shift and 1 add/sub except for the first
930 int32_t InstrRequired = 2 * NonzeroEntries - 1;
931 // Correct possible over-adding due to shift by 0 (which is not emitted).
933 --InstrRequired;
940 SDValue V = Op->getOperand(0);
945 if (HighestOne == -1)
964 else if (SignedDigit[I] == -1)
1008 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1013 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1064 const unsigned Offset = -4;
1071 // Mark it an implicit live-in.
1072 Register Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1085 while (Depth--) {
1086 const unsigned Offset = -8;
1130 const Constant *C = N->getConstVal();
1136 // then assume address will fit in 21-bits.
1138 TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1140 C, MVT::i32, N->getAlign(), N->getOffset(), LanaiII::MO_NO_FLAG);
1148 SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1149 N->getOffset(), OpFlagHi);
1150 SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1151 N->getOffset(), OpFlagLo);
1162 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1163 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1170 // section, then assume address will fit in 21-bits.
1171 const GlobalObject *GO = GV->getAliaseeObject();
1172 if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1196 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1214 // If the code model is small assume address will fit in 21-bits.
1217 JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
1226 JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1228 JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1247 // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1249 // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1296 // r_high = (32 - b <= 0) ? 0 : r_high;
1299 // r_low = (32 - b <= 0) ? r_high : r_low;
1300 // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1337 // (select cc -1, y) [AllOnes=1]
1338 // (select cc y, -1) [AllOnes=1]
1342 // * Invert is set when N is the all zero/ones constant when CC is false.
1346 // * X = 0, Invert = False and OtherOp = Y
1347 // * Y = 0, Invert = True and OtherOp = X
1349 bool &Invert, SDValue &OtherOp,
1351 switch (N->getOpcode()) {
1355 CC = N->getOperand(0);
1356 SDValue N1 = N->getOperand(1);
1357 SDValue N2 = N->getOperand(2);
1359 Invert = false;
1364 Invert = true;
1374 CC = N->getOperand(0);
1378 EVT VT = N->getValueType(0);
1380 Invert = true;
1384 CC = N->getOperand(0);
1388 EVT VT = N->getValueType(0);
1389 Invert = !AllOnes;
1403 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1404 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1405 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1406 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1407 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1414 // (add (zext cc), x) -> (select cc (add x, 1), x)
1415 // (add (sext cc), x) -> (select cc (add x, -1), x)
1422 EVT VT = N->getValueType(0);
1433 DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1445 SDValue N0 = N->getOperand(0);
1446 SDValue N1 = N->getOperand(1);
1447 if (N0.getNode()->hasOneUse())
1450 if (N1.getNode()->hasOneUse())
1456 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1459 SDValue N0 = N->getOperand(0);
1460 SDValue N1 = N->getOperand(1);
1462 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1463 if (N1.getNode()->hasOneUse())
1472 switch (N->getOpcode()) {
1501 Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
1502 Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);