Home
last modified time | relevance | path

Searched +full:fpga +full:- +full:bridge (Results 1 – 25 of 37) sorted by relevance

12

/freebsd-src/sys/contrib/device-tree/Bindings/fpga/
H A Dfpga-region.txt1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
[all …]
H A Daltera-hps2fpga-bridge.txt1 Altera FPGA/HPS Bridge Driver
4 - regs : base address and size for AXI bridge module
5 - compatible : Should contain one of:
6 "altr,socfpga-lwhps2fpga-bridge",
7 "altr,socfpga-hps2fpga-bridge", or
8 "altr,socfpga-fpga2hps-bridge"
9 - resets : Phandle and reset specifier for this bridge's reset
10 - clocks : Clocks used by this module.
12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
15 fpga_bridge0: fpga-bridge@ff400000 {
[all …]
H A Dxilinx-pr-decoupler.txt4 decouplers / fpga bridges.
6 changes from passing through the bridge. The controller can also
8 bridge normally.
11 Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
14 from passing through the bridge. The controller safely handles AXI4MM
15 and AXI4-Lite interfaces on a Reconfigurable Partition when it is
24 - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
25 "xlnx,pr-decoupler" or
26 "xlnx,dfx-axi-shutdown-manager-1.00" followed by
27 "xlnx,dfx-axi-shutdown-manager"
[all …]
H A Dfpga-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Bridge
10 - Michal Simek <michal.simek@amd.com>
14 pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
16 bridge-enable:
18 0 if driver should disable bridge at startup
19 1 if driver should enable bridge at startup
[all …]
H A Daltera-fpga2sdram-bridge.txt1 Altera FPGA To SDRAM Bridge Driver
4 - compatible : Should contain "altr,socfpga-fpga2sdram-bridge"
6 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
9 fpga_bridge3: fpga-bridge@ffc25080 {
10 compatible = "altr,socfpga-fpga2sdram-bridge";
12 bridge-enable = <0>;
H A Daltr,socfpga-hps2fpga-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera FPGA/HPS Bridge
10 - Xu Yilun <yilun.xu@intel.com>
13 - $ref: fpga-bridge.yaml#
18 - altr,socfpga-lwhps2fpga-bridge
19 - altr,socfpga-hps2fpga-bridge
20 - altr,socfpga-fpga2hps-bridge
[all …]
H A Daltr,socfpga-fpga2sdram-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera FPGA To SDRAM Bridge
10 - Xu Yilun <yilun.xu@intel.com>
13 - $ref: fpga-bridge.yaml#
17 const: altr,socfpga-fpga2sdram-bridge
23 - compatible
28 - |
[all …]
H A Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
17 decouplers/fpga bridges. The controller can decouple/disable the bridges
18 which prevents signal changes from passing through the bridge. The controller
20 bridge normally.
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
[all …]
H A Daltr,freeze-bridge-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera Freeze Bridge Controller
10 The Altera Freeze Bridge Controller manages one or more freeze bridges.
12 changes from passing through the bridge. The controller can also
13 unfreeze/enable the bridges which allows traffic to pass through the bridge
17 - Xu Yilun <yilun.xu@intel.com>
20 - $ref: fpga-bridge.yaml#
[all …]
H A Dfpga-bridge.txt1 FPGA Bridge Device Tree Binding
4 - bridge-enable : 0 if driver should disable bridge at startup
5 1 if driver should enable bridge at startup
6 Default is to leave bridge in current state.
9 fpga_bridge3: fpga-bridge@ffc25080 {
10 compatible = "altr,socfpga-fpga2sdram-bridge";
12 bridge-enable = <0>;
H A Daltera-freeze-bridge.txt1 Altera Freeze Bridge Controller Driver
3 The Altera Freeze Bridge Controller manages one or more freeze bridges.
5 changes from passing through the bridge. The controller can also
7 bridge normally.
10 - compatible : Should contain "altr,freeze-bridge-controller"
11 - regs : base address and size for freeze bridge module
13 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
16 freeze-controller@100000450 {
17 compatible = "altr,freeze-bridge-controller";
19 bridge-enable = <0>;
/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Dcurrituck.dts11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
[all …]
H A Dakebono.dts12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-lin
[all...]
H A Debony.dts14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <0>; // Filled in by zImage
39 timebase-frequency = <0>; // Filled in by zImage
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/arm/
H A Dvexpress-v2f-1xv7-ca53x2.dts1 // SPDX-License-Identifier: GPL-2.0
6 * V2F-1XV7
8 * Cortex-A53 (2 cores) Soft Macrocell Model
10 * HBI-0247C
13 /dts-v1/;
15 #include <dt-bindings/interrupt-controller/arm-gi
[all...]
/freebsd-src/sys/arm/altera/socfpga/
H A Dsocfpga_l3regs.h
/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dvexpress-config.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andre Przywara <andre.przywara@arm.com>
13 This is a system control register block, acting as a bridge to the
16 function and device numbers - see motherboard's TRM for more details.
20 const: arm,vexpress,config-bus
22 arm,vexpress,config-bridge:
31 const: arm,vexpress-muxfpga
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
11 compatible = "arm,integrator-cp";
18 #address-cells = <1>;
19 #size-cells = <0>;
35 operating-points = <50000 0
38 clock-names = "cpu";
39 clock-latenc
[all...]
H A Dversatile-ab.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 compatible = "arm,versatile-ab";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
19 stdout-path = &uart0;
27 xtal24mhz: clock-2400000
[all...]
H A Dintegratorap.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "arm,integrator-ap";
16 #address-cells = <1>;
17 #size-cells = <0>;
27 /* compatible = "arm,arm926ej-
[all...]
/freebsd-src/share/misc/
H A Dpci_vendors5 # Date: 2024-11-25 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-250
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Dmicrochip,pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-hos
[all...]
/freebsd-src/sys/dev/bhnd/
H A Dbhnd_ids.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 1999-2015, Broadcom Corporation
9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's
30 * JEDEC JEP-106 Core Vendor IDs
32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's
33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell
38 * will need to convert bus-specific vendor IDs to their BHND_MFGID
39 * JEP-106 equivalents.
[all …]
/freebsd-src/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8548cds.dtsi2 * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
46 label = "ramdisk-nor";
51 label = "kernel-nor";
56 label = "dtb-nor";
61 label = "env-nor";
[all …]

12