1*8d13bc63SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*8d13bc63SEmmanuel Vadot%YAML 1.2 3*8d13bc63SEmmanuel Vadot--- 4*8d13bc63SEmmanuel Vadot$id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml# 5*8d13bc63SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*8d13bc63SEmmanuel Vadot 7*8d13bc63SEmmanuel Vadottitle: Altera FPGA/HPS Bridge 8*8d13bc63SEmmanuel Vadot 9*8d13bc63SEmmanuel Vadotmaintainers: 10*8d13bc63SEmmanuel Vadot - Xu Yilun <yilun.xu@intel.com> 11*8d13bc63SEmmanuel Vadot 12*8d13bc63SEmmanuel VadotallOf: 13*8d13bc63SEmmanuel Vadot - $ref: fpga-bridge.yaml# 14*8d13bc63SEmmanuel Vadot 15*8d13bc63SEmmanuel Vadotproperties: 16*8d13bc63SEmmanuel Vadot compatible: 17*8d13bc63SEmmanuel Vadot enum: 18*8d13bc63SEmmanuel Vadot - altr,socfpga-lwhps2fpga-bridge 19*8d13bc63SEmmanuel Vadot - altr,socfpga-hps2fpga-bridge 20*8d13bc63SEmmanuel Vadot - altr,socfpga-fpga2hps-bridge 21*8d13bc63SEmmanuel Vadot 22*8d13bc63SEmmanuel Vadot reg: 23*8d13bc63SEmmanuel Vadot maxItems: 1 24*8d13bc63SEmmanuel Vadot 25*8d13bc63SEmmanuel Vadot resets: 26*8d13bc63SEmmanuel Vadot maxItems: 1 27*8d13bc63SEmmanuel Vadot 28*8d13bc63SEmmanuel Vadot clocks: 29*8d13bc63SEmmanuel Vadot maxItems: 1 30*8d13bc63SEmmanuel Vadot 31*8d13bc63SEmmanuel Vadotrequired: 32*8d13bc63SEmmanuel Vadot - compatible 33*8d13bc63SEmmanuel Vadot - reg 34*8d13bc63SEmmanuel Vadot - clocks 35*8d13bc63SEmmanuel Vadot - resets 36*8d13bc63SEmmanuel Vadot 37*8d13bc63SEmmanuel VadotunevaluatedProperties: false 38*8d13bc63SEmmanuel Vadot 39*8d13bc63SEmmanuel Vadotexamples: 40*8d13bc63SEmmanuel Vadot - | 41*8d13bc63SEmmanuel Vadot #include <dt-bindings/reset/altr,rst-mgr.h> 42*8d13bc63SEmmanuel Vadot 43*8d13bc63SEmmanuel Vadot fpga-bridge@ff400000 { 44*8d13bc63SEmmanuel Vadot compatible = "altr,socfpga-lwhps2fpga-bridge"; 45*8d13bc63SEmmanuel Vadot reg = <0xff400000 0x100000>; 46*8d13bc63SEmmanuel Vadot bridge-enable = <0>; 47*8d13bc63SEmmanuel Vadot clocks = <&l4_main_clk>; 48*8d13bc63SEmmanuel Vadot resets = <&rst LWHPS2FPGA_RESET>; 49*8d13bc63SEmmanuel Vadot }; 50