Lines Matching +full:fpga +full:- +full:bridge
2 * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
46 label = "ramdisk-nor";
51 label = "kernel-nor";
56 label = "dtb-nor";
61 label = "env-nor";
62 read-only;
67 label = "u-boot-nor";
68 read-only;
72 board-control@1,0 {
73 compatible = "fsl,mpc8548cds-fpga";
104 tbi-handle = <&tbi0>;
105 phy-handle = <&phy0>;
109 phy0: ethernet-phy@0 {
113 phy1: ethernet-phy@1 {
117 phy2: ethernet-phy@2 {
121 phy3: ethernet-phy@3 {
125 tbi0: tbi-phy@11 {
127 device_type = "tbi-phy";
132 tbi-handle = <&tbi1>;
133 phy-handle = <&phy1>;
137 tbi1: tbi-phy@11 {
139 device_type = "tbi-phy";
144 tbi-handle = <&tbi2>;
145 phy-handle = <&phy2>;
149 tbi2: tbi-phy@11 {
151 device_type = "tbi-phy";
156 tbi-handle = <&tbi3>;
157 phy-handle = <&phy3>;
161 tbi3: tbi-phy@11 {
163 device_type = "tbi-phy";
169 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
170 interrupt-map = <
195 /* IDSEL 0xC (Tsi310 bridge) */
225 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
232 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
233 interrupt-map = <
263 #interrupt-cells = <1>;
264 #size-cells = <2>;
265 #address-cells = <3>;
272 clock-frequency = <33333333>;
276 #interrupt-cells = <2>;
277 #size-cells = <1>;
278 #address-cells = <2>;
281 interrupt-parent = <&i8259>;
283 i8259: interrupt-controller@20 {
284 interrupt-controller;
285 device_type = "interrupt-controller";
289 #address-cells = <0>;
290 #interrupt-cells = <2>;
293 interrupt-parent = <&mpic>;