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/freebsd-src/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddivider.txt28 Additionally an array of valid dividers may be supplied like so:
30 ti,dividers = <4>, <8>, <0>, <16>;
43 unless the divider array is provided, min and max dividers. Optionally
61 - ti,dividers : array of integers defining divisors
66 if ti,dividers is not defined.
68 only valid if ti,dividers is not defined.
70 only valid if ti,dividers is not defined.
114 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dbaikal,bt1-ccu-div.yaml8 title: Baikal-T1 Clock Control Unit Dividers
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
26 3) AXI-bus clock dividers (AXI) - described in this binding file.
27 4) System devices reference clock dividers (SYS) - described in this binding
51 then passed over CCU dividers to create signals required for the target clock
52 domain (like AXI-bus or System Device consumers). The dividers have the
71 peculiarities the dividers may lack of some functionality depicted on the
76 The clock dividers, which output clock is then consumed by the SoC individual
78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
H A Dbaikal,bt1-ccu-pll.yaml19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
24 3) AXI-bus clock dividers (AXI).
25 4) System devices reference clock dividers (SYS).
73 the binding supports the PLL dividers configuration in accordance with a
H A Ddove-divider-clock.txt3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
4 high speed clocks for a number of peripherals. These dividers are part of
H A Dmediatek,mt8188-sys-clock.yaml15 dividers -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
H A Dbrcm,bcm2835-cprman.txt8 oscillator, a level of PLL dividers that produce channels off of the
12 the PLL dividers directly.
H A Drenesas,r8a73a4-cpg-clocks.txt4 and several fixed ratio dividers.
H A Drenesas,sh73a0-cpg-clocks.txt6 and several fixed ratio dividers.
H A Dmediatek,mt8365-sys-clock.yaml14 The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
/freebsd-src/sys/arm64/qoriq/clk/
H A Dqoriq_clk_pll.c136 while (clkdef->dividers[i] != 0) { in qoriq_clk_pll_register()
137 def.div = clkdef->dividers[i]; in qoriq_clk_pll_register()
140 parent_name, clkdef->dividers[i]); in qoriq_clk_pll_register()
H A Dls1046a_clkgen.c59 .dividers = ls1046a_pltfrm_pll_divs,
76 .dividers = ls1046a_cga1_pll_divs,
89 .dividers = ls1046a_cga1_pll_divs,
H A Dls1088a_clkgen.c64 .dividers = ls1088a_pltfrm_pll_divs,
81 .dividers = ls1088a_cga_pll_divs,
94 .dividers = ls1088a_cga_pll_divs,
H A Dls1028a_clkgen.c59 .dividers = ls1028a_pltfrm_pll_divs,
76 .dividers = ls1028a_cga_pll_divs,
89 .dividers = ls1028a_cga_pll_divs,
/freebsd-src/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mt8186-sys-clock.yaml15 dividers -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
H A Dmediatek,mt8195-sys-clock.yaml15 dividers -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
/freebsd-src/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dexynos3250.h82 /* Dividers */
273 /* Dividers */
284 /* Dividers */
H A Dingenic,jz4740-cgu.h8 * - muxes/dividers in the order they appear in the jz4740 programmers manual
H A Djz4740-cgu.h8 * - muxes/dividers in the order they appear in the jz4740 programmers manual
H A Dx1000-cgu.h8 * - muxes/dividers in the order they appear in the x1000 programmers manual
H A Dx1830-cgu.h8 * - muxes/dividers in the order they appear in the x1830 programmers manual
H A Dingenic,x1000-cgu.h8 * - muxes/dividers in the order they appear in the x1000 programmers manual
H A Dingenic,x1830-cgu.h8 * - muxes/dividers in the order they appear in the x1830 programmers manual
/freebsd-src/sys/contrib/device-tree/Bindings/clock/st/
H A Dst,flexgen.txt6 - a pre and final dividers (represented by a divider and gate elements)
21 | | |PLL0 | | | | |Dividers| |Dividers| | |
/freebsd-src/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap2420-clocks.dtsi79 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
262 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
266 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
H A Domap446x-clocks.dtsi15 ti,dividers = <8>, <16>, <32>;

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