xref: /freebsd-src/sys/contrib/device-tree/include/dt-bindings/clock/x1000-cgu.h (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */
2*c66ec88fSEmmanuel Vadot /*
3*c66ec88fSEmmanuel Vadot  * This header provides clock numbers for the ingenic,x1000-cgu DT binding.
4*c66ec88fSEmmanuel Vadot  *
5*c66ec88fSEmmanuel Vadot  * They are roughly ordered as:
6*c66ec88fSEmmanuel Vadot  *   - external clocks
7*c66ec88fSEmmanuel Vadot  *   - PLLs
8*c66ec88fSEmmanuel Vadot  *   - muxes/dividers in the order they appear in the x1000 programmers manual
9*c66ec88fSEmmanuel Vadot  *   - gates in order of their bit in the CLKGR* registers
10*c66ec88fSEmmanuel Vadot  */
11*c66ec88fSEmmanuel Vadot 
12*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
13*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_X1000_CGU_H__
14*c66ec88fSEmmanuel Vadot 
15*c66ec88fSEmmanuel Vadot #define X1000_CLK_EXCLK			0
16*c66ec88fSEmmanuel Vadot #define X1000_CLK_RTCLK			1
17*c66ec88fSEmmanuel Vadot #define X1000_CLK_APLL			2
18*c66ec88fSEmmanuel Vadot #define X1000_CLK_MPLL			3
19*c66ec88fSEmmanuel Vadot #define X1000_CLK_OTGPHY		4
20*c66ec88fSEmmanuel Vadot #define X1000_CLK_SCLKA			5
21*c66ec88fSEmmanuel Vadot #define X1000_CLK_CPUMUX		6
22*c66ec88fSEmmanuel Vadot #define X1000_CLK_CPU			7
23*c66ec88fSEmmanuel Vadot #define X1000_CLK_L2CACHE		8
24*c66ec88fSEmmanuel Vadot #define X1000_CLK_AHB0			9
25*c66ec88fSEmmanuel Vadot #define X1000_CLK_AHB2PMUX		10
26*c66ec88fSEmmanuel Vadot #define X1000_CLK_AHB2			11
27*c66ec88fSEmmanuel Vadot #define X1000_CLK_PCLK			12
28*c66ec88fSEmmanuel Vadot #define X1000_CLK_DDR			13
29*c66ec88fSEmmanuel Vadot #define X1000_CLK_MAC			14
30*c66ec88fSEmmanuel Vadot #define X1000_CLK_LCD			15
31*c66ec88fSEmmanuel Vadot #define X1000_CLK_MSCMUX		16
32*c66ec88fSEmmanuel Vadot #define X1000_CLK_MSC0			17
33*c66ec88fSEmmanuel Vadot #define X1000_CLK_MSC1			18
34*c66ec88fSEmmanuel Vadot #define X1000_CLK_OTG			19
35*c66ec88fSEmmanuel Vadot #define X1000_CLK_SSIPLL		20
36*c66ec88fSEmmanuel Vadot #define X1000_CLK_SSIPLL_DIV2	21
37*c66ec88fSEmmanuel Vadot #define X1000_CLK_SSIMUX		22
38*c66ec88fSEmmanuel Vadot #define X1000_CLK_EMC			23
39*c66ec88fSEmmanuel Vadot #define X1000_CLK_EFUSE			24
40*c66ec88fSEmmanuel Vadot #define X1000_CLK_SFC			25
41*c66ec88fSEmmanuel Vadot #define X1000_CLK_I2C0			26
42*c66ec88fSEmmanuel Vadot #define X1000_CLK_I2C1			27
43*c66ec88fSEmmanuel Vadot #define X1000_CLK_I2C2			28
44*c66ec88fSEmmanuel Vadot #define X1000_CLK_UART0			29
45*c66ec88fSEmmanuel Vadot #define X1000_CLK_UART1			30
46*c66ec88fSEmmanuel Vadot #define X1000_CLK_UART2			31
47*c66ec88fSEmmanuel Vadot #define X1000_CLK_TCU			32
48*c66ec88fSEmmanuel Vadot #define X1000_CLK_SSI			33
49*c66ec88fSEmmanuel Vadot #define X1000_CLK_OST			34
50*c66ec88fSEmmanuel Vadot #define X1000_CLK_PDMA			35
51*c66ec88fSEmmanuel Vadot #define X1000_CLK_EXCLK_DIV512	36
52*c66ec88fSEmmanuel Vadot #define X1000_CLK_RTC			37
53*c66ec88fSEmmanuel Vadot 
54*c66ec88fSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
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