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/llvm-project/llvm/test/MC/ARM/
H A Dneon-bitwise-encoding.s176 vand d4, d7, d3
177 vand.8 d4, d7, d3
178 vand.16 d4, d7, d3
179 vand.32 d4, d7, d3
180 vand.64 d4, d7, d3
182 vand.i8 d4, d7, d3
183 vand.i16 d4, d7, d3
184 vand.i32 d4, d7, d3
185 vand.i64 d4, d7, d3
187 vand.s8 d4, d7, d3
[all …]
H A Dsingle-precision-fp.s8 vmul.f64 d6, d7, d8
17 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
22 vmls.f64 d8, d7, d6
27 vfnma.f64 d7, d8, d9
32 @ CHECK-ERRORS-NEXT: vmls.f64 d8, d7, d6
42 @ CHECK-ERRORS-NEXT: vfnma.f64 d7, d8, d9
79 vcvt.f64.u32 d7, s6
86 vcvt.s32.f64 d7, d8, #3
95 @ CHECK-ERRORS-NEXT: vcvt.f64.u32 d7, s6
109 @ CHECK-ERRORS-NEXT: vcvt.s32.f64 d7, d8, #3
[all …]
H A Dneon-vld-encoding.s13 vld1.32 {d5, d6, d7}, [r3]
14 vld1.64 {d6, d7, d8}, [r3:64]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
18 vld1.64 {d6, d7, d8, d9}, [r3:64]
40 vld1.32 {d5, d6, d7}, [r3]!
41 vld1.64 {d6, d7, d8}, [r3:64]!
45 vld1.32 {d5, d6, d7}, [r3], r6
46 vld1.64 {d6, d7, d8}, [r3:64], r6
49 vld1.16 {d4, d5, d6, d7}, [r3:64]!
[all …]
H A Dneon-mul-accum-encoding.s41 vqdmlal.s16 q11, d11, d7[0]
42 vqdmlal.s16 q11, d11, d7[1]
43 vqdmlal.s16 q11, d11, d7[2]
44 vqdmlal.s16 q11, d11, d7[3]
48 @ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0x47,0x63,0xdb,0xf2]
49 @ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0x4f,0x63,0xdb,0xf2]
50 @ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0x67,0x63,0xdb,0xf2]
51 @ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0x6f,0x63,0xdb,0xf2]
H A Dneont2-mul-accum-encoding.s45 vqdmlal.s16 q11, d11, d7[0]
46 vqdmlal.s16 q11, d11, d7[1]
47 vqdmlal.s16 q11, d11, d7[2]
48 vqdmlal.s16 q11, d11, d7[3]
52 @ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0xdb,0xef,0x47,0x63]
53 @ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0xdb,0xef,0x4f,0x63]
54 @ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0xdb,0xef,0x67,0x63]
55 @ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0xdb,0xef,0x6f,0x63]
/llvm-project/libcxx/test/libcxx/containers/strings/basic.string/
H A Dasan_vector_integration.pass.cpp133 C d7(9 * N + 2); in test_string() local
135 d7.insert(d7.begin() + 1, S()); in test_string()
136 verify_inside(d7); in test_string()
138 d7.insert(d7.end() - 3, S()); in test_string()
139 verify_inside(d7); in test_string()
141 d7.insert(d7.begin() + 2 * N, get_s<S, 1>('a')); in test_string()
142 verify_inside(d7); in test_string()
144 d7.insert(d7.end() - 2 * N, get_s<S, 1>('b')); in test_string()
145 verify_inside(d7); in test_string()
147 d7.insert(d7.begin() + 2 * N, 3 * N, get_s<S, 1>('c')); in test_string()
[all …]
H A Dasan_deque_integration.pass.cpp133 C d7(9 * N + 2); in test_string() local
135 d7.insert(d7.begin() + 1, S()); in test_string()
136 verify_inside(d7); in test_string()
138 d7.insert(d7.end() - 3, S()); in test_string()
139 verify_inside(d7); in test_string()
141 d7.insert(d7.begin() + 2 * N, get_s<S, 1>('a')); in test_string()
142 verify_inside(d7); in test_string()
144 d7.insert(d7.end() - 2 * N, get_s<S, 1>('b')); in test_string()
145 verify_inside(d7); in test_string()
147 d7.insert(d7.begin() + 2 * N, 3 * N, get_s<S, 1>('c')); in test_string()
[all …]
/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dfcmp.mir605 liveins: $d6, $d7
608 ; FP32: liveins: $d6, $d7
613 ; FP64: liveins: $d6, $d7
631 liveins: $d6, $d7
634 ; FP32: liveins: $d6, $d7
639 ; FP64: liveins: $d6, $d7
657 liveins: $d6, $d7
660 ; FP32: liveins: $d6, $d7
662 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
669 ; FP64: liveins: $d6, $d7
[all …]
H A Dfloat_arithmetic_operations.mir148 liveins: $d6, $d7
151 ; FP32: liveins: $d6, $d7
153 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
158 ; FP64: liveins: $d6, $d7
160 ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
165 %1:fprb(s64) = COPY $d7
179 liveins: $d6, $d7
182 ; FP32: liveins: $d6, $d7
184 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
189 ; FP64: liveins: $d6, $d7
[all …]
H A Dfloat_args.mir49 liveins: $d6, $d7
52 ; FP32: liveins: $d6, $d7
53 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d7
57 ; FP64: liveins: $d6, $d7
58 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d7
61 %1:fprb(s64) = COPY $d7
176 liveins: $d6, $d7
179 ; FP32: liveins: $d6, $d7
181 ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
184 ; FP32: $d7 = COPY [[COPY1]]
[all …]
/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfloat_arithmetic_operations.mir139 liveins: $d6, $d7
142 ; FP32: liveins: $d6, $d7
144 ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
149 ; FP64: liveins: $d6, $d7
151 ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
156 %1:_(s64) = COPY $d7
168 liveins: $d6, $d7
171 ; FP32: liveins: $d6, $d7
173 ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
178 ; FP64: liveins: $d6, $d7
[all …]
H A Dfcmp.mir46 liveins: $d6, $d7
49 ; FP32: liveins: $d6, $d7
51 ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
56 ; FP64: liveins: $d6, $d7
58 ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
63 %1:_(s64) = COPY $d7
/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir144 liveins: $d6, $d7
147 ; FP32: liveins: $d6, $d7
149 ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
154 ; FP64: liveins: $d6, $d7
156 ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
161 %1:_(s64) = COPY $d7
174 liveins: $d6, $d7
177 ; FP32: liveins: $d6, $d7
179 ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
184 ; FP64: liveins: $d6, $d7
[all …]
H A Dfloat_args.mir48 liveins: $d6, $d7
51 ; FP32: liveins: $d6, $d7
52 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d7
56 ; FP64: liveins: $d6, $d7
57 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d7
60 %1:_(s64) = COPY $d7
171 liveins: $d6, $d7
174 ; FP32: liveins: $d6, $d7
176 ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
179 ; FP32: $d7 = COPY [[COPY1]](s64)
[all …]
H A Dfcmp.mir50 liveins: $d6, $d7
53 ; FP32: liveins: $d6, $d7
55 ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
61 ; FP64: liveins: $d6, $d7
63 ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
69 %1:_(s64) = COPY $d7
/llvm-project/clang/test/CodeGen/
H A Daarch64-ABI-align-packed-assembly.c
H A Daarch64-ABI-align-packed.c
/llvm-project/llvm/test/tools/llvm-profgen/Inputs/
H A Dcold-profile-trimming.raw.prof25 4007cf-4007d7:12
26 4007d7-4007d7:12
46 400792->4007d7:12
51 4007d7->4007bd:12
52 4007d7->4007cf:13
/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dpost-ra-kill-update.mir9 # CHECK: $d7 = S2_lsr_r_p_or killed $d7, killed $d1, $r9
26 $d7 = S2_asl_r_p $d0, $r13
29 $d7 = S2_lsr_r_p_or killed $d7, killed $d1, killed $r9
/llvm-project/llvm/test/CodeGen/Mips/longbranch/
H A Dbranch-limits-fp-micromips.mir48 - { reg: '$d7', virtual-reg: '' }
74 ; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
93 ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
121 liveins: $d6, $d7
123 FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
148 - { reg: '$d7', virtual-reg: '' }
174 ; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
188 ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
201 liveins: $d6, $d7
203 FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
H A Dbranch-limits-fp-mips.mir47 - { reg: '$d7', virtual-reg: '' }
73 ; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
94 ; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
124 liveins: $d6, $d7
126 FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
151 - { reg: '$d7', virtual-reg: '' }
177 ; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
198 ; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
228 liveins: $d6, $d7
230 FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
/llvm-project/llvm/test/CodeGen/X86/
H A Dfp128-calling-conv.ll10 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
18 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
27 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
33 ret fp128 %d7
36 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
45 …, fp128 %d1, fp128 %d2, fp128 %d3, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d…
/llvm-project/llvm/test/CodeGen/ARM/
H A Dv6-jumptable-clobber.mir34 i32 7, label %d7
68 d7: ; preds = %0
112 i32 7, label %d7
146 d7: ; preds = %0
223 '%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9',
243 …), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.…
263 bb.8.d7:
321 '%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9',
340 …), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.…
360 bb.8.d7:
/llvm-project/clang/test/CXX/special/class.inhctor/
H A Dp7.cpp43 struct D7 : B5 { struct
45 template<typename T> D7(T, ...);
48 D7 d7(0); variable
/llvm-project/compiler-rt/lib/builtins/arm/
H A Dfloatsidfvfp.S26 vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
27 VMOV_FROM_DOUBLE(r0, r1, d7) // move d7 to result register pair r0/r1

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