xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir (revision 48904e9452de81375bd55d830d08e51cc8f2ec7e) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
3# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
4--- |
5
6  define void @float_add() {entry: ret void}
7  define void @float_sub() {entry: ret void}
8  define void @float_mul() {entry: ret void}
9  define void @float_div() {entry: ret void}
10  define void @double_add() {entry: ret void}
11  define void @double_sub() {entry: ret void}
12  define void @double_mul() {entry: ret void}
13  define void @double_div() {entry: ret void}
14
15...
16---
17name:            float_add
18alignment:       4
19legalized:       true
20regBankSelected: true
21tracksRegLiveness: true
22body:             |
23  bb.1.entry:
24    liveins: $f12, $f14
25
26    ; FP32-LABEL: name: float_add
27    ; FP32: liveins: $f12, $f14
28    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
29    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
30    ; FP32: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
31    ; FP32: $f0 = COPY [[FADD_S]]
32    ; FP32: RetRA implicit $f0
33    ; FP64-LABEL: name: float_add
34    ; FP64: liveins: $f12, $f14
35    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
36    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
37    ; FP64: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
38    ; FP64: $f0 = COPY [[FADD_S]]
39    ; FP64: RetRA implicit $f0
40    %0:fprb(s32) = COPY $f12
41    %1:fprb(s32) = COPY $f14
42    %2:fprb(s32) = G_FADD %0, %1
43    $f0 = COPY %2(s32)
44    RetRA implicit $f0
45
46...
47---
48name:            float_sub
49alignment:       4
50legalized:       true
51regBankSelected: true
52tracksRegLiveness: true
53body:             |
54  bb.1.entry:
55    liveins: $f12, $f14
56
57    ; FP32-LABEL: name: float_sub
58    ; FP32: liveins: $f12, $f14
59    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
60    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
61    ; FP32: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
62    ; FP32: $f0 = COPY [[FSUB_S]]
63    ; FP32: RetRA implicit $f0
64    ; FP64-LABEL: name: float_sub
65    ; FP64: liveins: $f12, $f14
66    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
67    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
68    ; FP64: [[FSUB_S:%[0-9]+]]:fgr32 = FSUB_S [[COPY]], [[COPY1]]
69    ; FP64: $f0 = COPY [[FSUB_S]]
70    ; FP64: RetRA implicit $f0
71    %0:fprb(s32) = COPY $f12
72    %1:fprb(s32) = COPY $f14
73    %2:fprb(s32) = G_FSUB %0, %1
74    $f0 = COPY %2(s32)
75    RetRA implicit $f0
76
77...
78---
79name:            float_mul
80alignment:       4
81legalized:       true
82regBankSelected: true
83tracksRegLiveness: true
84body:             |
85  bb.1.entry:
86    liveins: $f12, $f14
87
88    ; FP32-LABEL: name: float_mul
89    ; FP32: liveins: $f12, $f14
90    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
91    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
92    ; FP32: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
93    ; FP32: $f0 = COPY [[FMUL_S]]
94    ; FP32: RetRA implicit $f0
95    ; FP64-LABEL: name: float_mul
96    ; FP64: liveins: $f12, $f14
97    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
98    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
99    ; FP64: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
100    ; FP64: $f0 = COPY [[FMUL_S]]
101    ; FP64: RetRA implicit $f0
102    %0:fprb(s32) = COPY $f12
103    %1:fprb(s32) = COPY $f14
104    %2:fprb(s32) = G_FMUL %0, %1
105    $f0 = COPY %2(s32)
106    RetRA implicit $f0
107
108...
109---
110name:            float_div
111alignment:       4
112legalized:       true
113regBankSelected: true
114tracksRegLiveness: true
115body:             |
116  bb.1.entry:
117    liveins: $f12, $f14
118
119    ; FP32-LABEL: name: float_div
120    ; FP32: liveins: $f12, $f14
121    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
122    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
123    ; FP32: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
124    ; FP32: $f0 = COPY [[FDIV_S]]
125    ; FP32: RetRA implicit $f0
126    ; FP64-LABEL: name: float_div
127    ; FP64: liveins: $f12, $f14
128    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
129    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
130    ; FP64: [[FDIV_S:%[0-9]+]]:fgr32 = FDIV_S [[COPY]], [[COPY1]]
131    ; FP64: $f0 = COPY [[FDIV_S]]
132    ; FP64: RetRA implicit $f0
133    %0:fprb(s32) = COPY $f12
134    %1:fprb(s32) = COPY $f14
135    %2:fprb(s32) = G_FDIV %0, %1
136    $f0 = COPY %2(s32)
137    RetRA implicit $f0
138
139...
140---
141name:            double_add
142alignment:       4
143legalized:       true
144regBankSelected: true
145tracksRegLiveness: true
146body:             |
147  bb.1.entry:
148    liveins: $d6, $d7
149
150    ; FP32-LABEL: name: double_add
151    ; FP32: liveins: $d6, $d7
152    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
153    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
154    ; FP32: [[FADD_D32_:%[0-9]+]]:afgr64 = FADD_D32 [[COPY]], [[COPY1]]
155    ; FP32: $d0 = COPY [[FADD_D32_]]
156    ; FP32: RetRA implicit $d0
157    ; FP64-LABEL: name: double_add
158    ; FP64: liveins: $d6, $d7
159    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
160    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
161    ; FP64: [[FADD_D64_:%[0-9]+]]:fgr64 = FADD_D64 [[COPY]], [[COPY1]]
162    ; FP64: $d0 = COPY [[FADD_D64_]]
163    ; FP64: RetRA implicit $d0
164    %0:fprb(s64) = COPY $d6
165    %1:fprb(s64) = COPY $d7
166    %2:fprb(s64) = G_FADD %0, %1
167    $d0 = COPY %2(s64)
168    RetRA implicit $d0
169
170...
171---
172name:            double_sub
173alignment:       4
174legalized:       true
175regBankSelected: true
176tracksRegLiveness: true
177body:             |
178  bb.1.entry:
179    liveins: $d6, $d7
180
181    ; FP32-LABEL: name: double_sub
182    ; FP32: liveins: $d6, $d7
183    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
184    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
185    ; FP32: [[FSUB_D32_:%[0-9]+]]:afgr64 = FSUB_D32 [[COPY]], [[COPY1]]
186    ; FP32: $d0 = COPY [[FSUB_D32_]]
187    ; FP32: RetRA implicit $d0
188    ; FP64-LABEL: name: double_sub
189    ; FP64: liveins: $d6, $d7
190    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
191    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
192    ; FP64: [[FSUB_D64_:%[0-9]+]]:fgr64 = FSUB_D64 [[COPY]], [[COPY1]]
193    ; FP64: $d0 = COPY [[FSUB_D64_]]
194    ; FP64: RetRA implicit $d0
195    %0:fprb(s64) = COPY $d6
196    %1:fprb(s64) = COPY $d7
197    %2:fprb(s64) = G_FSUB %0, %1
198    $d0 = COPY %2(s64)
199    RetRA implicit $d0
200
201...
202---
203name:            double_mul
204alignment:       4
205legalized:       true
206regBankSelected: true
207tracksRegLiveness: true
208body:             |
209  bb.1.entry:
210    liveins: $d6, $d7
211
212    ; FP32-LABEL: name: double_mul
213    ; FP32: liveins: $d6, $d7
214    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
215    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
216    ; FP32: [[FMUL_D32_:%[0-9]+]]:afgr64 = FMUL_D32 [[COPY]], [[COPY1]]
217    ; FP32: $d0 = COPY [[FMUL_D32_]]
218    ; FP32: RetRA implicit $d0
219    ; FP64-LABEL: name: double_mul
220    ; FP64: liveins: $d6, $d7
221    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
222    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
223    ; FP64: [[FMUL_D64_:%[0-9]+]]:fgr64 = FMUL_D64 [[COPY]], [[COPY1]]
224    ; FP64: $d0 = COPY [[FMUL_D64_]]
225    ; FP64: RetRA implicit $d0
226    %0:fprb(s64) = COPY $d6
227    %1:fprb(s64) = COPY $d7
228    %2:fprb(s64) = G_FMUL %0, %1
229    $d0 = COPY %2(s64)
230    RetRA implicit $d0
231
232...
233---
234name:            double_div
235alignment:       4
236legalized:       true
237regBankSelected: true
238tracksRegLiveness: true
239body:             |
240  bb.1.entry:
241    liveins: $d6, $d7
242
243    ; FP32-LABEL: name: double_div
244    ; FP32: liveins: $d6, $d7
245    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
246    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
247    ; FP32: [[FDIV_D32_:%[0-9]+]]:afgr64 = FDIV_D32 [[COPY]], [[COPY1]]
248    ; FP32: $d0 = COPY [[FDIV_D32_]]
249    ; FP32: RetRA implicit $d0
250    ; FP64-LABEL: name: double_div
251    ; FP64: liveins: $d6, $d7
252    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
253    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
254    ; FP64: [[FDIV_D64_:%[0-9]+]]:fgr64 = FDIV_D64 [[COPY]], [[COPY1]]
255    ; FP64: $d0 = COPY [[FDIV_D64_]]
256    ; FP64: RetRA implicit $d0
257    %0:fprb(s64) = COPY $d6
258    %1:fprb(s64) = COPY $d7
259    %2:fprb(s64) = G_FDIV %0, %1
260    $d0 = COPY %2(s64)
261    RetRA implicit $d0
262
263...
264