xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir (revision 48904e9452de81375bd55d830d08e51cc8f2ec7e) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
3# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
4--- |
5
6  define void @false_s() {entry: ret void}
7  define void @true_s() {entry: ret void}
8  define void @uno_s() {entry: ret void}
9  define void @ord_s() {entry: ret void}
10  define void @oeq_s() {entry: ret void}
11  define void @une_s() {entry: ret void}
12  define void @ueq_s() {entry: ret void}
13  define void @one_s() {entry: ret void}
14  define void @olt_s() {entry: ret void}
15  define void @uge_s() {entry: ret void}
16  define void @ult_s() {entry: ret void}
17  define void @oge_s() {entry: ret void}
18  define void @ole_s() {entry: ret void}
19  define void @ugt_s() {entry: ret void}
20  define void @ule_s() {entry: ret void}
21  define void @ogt_s() {entry: ret void}
22
23  define void @false_d() {entry: ret void}
24  define void @true_d() {entry: ret void}
25  define void @uno_d() {entry: ret void}
26  define void @ord_d() {entry: ret void}
27  define void @oeq_d() {entry: ret void}
28  define void @une_d() {entry: ret void}
29  define void @ueq_d() {entry: ret void}
30  define void @one_d() {entry: ret void}
31  define void @olt_d() {entry: ret void}
32  define void @uge_d() {entry: ret void}
33  define void @ult_d() {entry: ret void}
34  define void @oge_d() {entry: ret void}
35  define void @ole_d() {entry: ret void}
36  define void @ugt_d() {entry: ret void}
37  define void @ule_d() {entry: ret void}
38  define void @ogt_d() {entry: ret void}
39
40...
41---
42name:            false_s
43alignment:       4
44legalized:       true
45regBankSelected: true
46tracksRegLiveness: true
47body:             |
48  bb.1.entry:
49    liveins: $f12, $f14
50
51    ; FP32-LABEL: name: false_s
52    ; FP32: liveins: $f12, $f14
53    ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
54    ; FP32: $v0 = COPY [[ORi]]
55    ; FP32: RetRA implicit $v0
56    ; FP64-LABEL: name: false_s
57    ; FP64: liveins: $f12, $f14
58    ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
59    ; FP64: $v0 = COPY [[ORi]]
60    ; FP64: RetRA implicit $v0
61    %5:gprb(s32) = G_CONSTANT i32 0
62    %4:gprb(s32) = COPY %5(s32)
63    $v0 = COPY %4(s32)
64    RetRA implicit $v0
65
66...
67---
68name:            true_s
69alignment:       4
70legalized:       true
71regBankSelected: true
72tracksRegLiveness: true
73body:             |
74  bb.1.entry:
75    liveins: $f12, $f14
76
77    ; FP32-LABEL: name: true_s
78    ; FP32: liveins: $f12, $f14
79    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
80    ; FP32: $v0 = COPY [[ADDiu]]
81    ; FP32: RetRA implicit $v0
82    ; FP64-LABEL: name: true_s
83    ; FP64: liveins: $f12, $f14
84    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
85    ; FP64: $v0 = COPY [[ADDiu]]
86    ; FP64: RetRA implicit $v0
87    %5:gprb(s32) = G_CONSTANT i32 -1
88    %4:gprb(s32) = COPY %5(s32)
89    $v0 = COPY %4(s32)
90    RetRA implicit $v0
91
92...
93---
94name:            uno_s
95alignment:       4
96legalized:       true
97regBankSelected: true
98tracksRegLiveness: true
99body:             |
100  bb.1.entry:
101    liveins: $f12, $f14
102
103    ; FP32-LABEL: name: uno_s
104    ; FP32: liveins: $f12, $f14
105    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
106    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
107    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
108    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
109    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
110    ; FP32: $v0 = COPY [[MOVF_I]]
111    ; FP32: RetRA implicit $v0
112    ; FP64-LABEL: name: uno_s
113    ; FP64: liveins: $f12, $f14
114    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
115    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
116    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
117    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
118    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
119    ; FP64: $v0 = COPY [[MOVF_I]]
120    ; FP64: RetRA implicit $v0
121    %0:fprb(s32) = COPY $f12
122    %1:fprb(s32) = COPY $f14
123    %4:gprb(s32) = G_FCMP floatpred(uno), %0(s32), %1
124    %3:gprb(s32) = COPY %4(s32)
125    $v0 = COPY %3(s32)
126    RetRA implicit $v0
127
128...
129---
130name:            ord_s
131alignment:       4
132legalized:       true
133regBankSelected: true
134tracksRegLiveness: true
135body:             |
136  bb.1.entry:
137    liveins: $f12, $f14
138
139    ; FP32-LABEL: name: ord_s
140    ; FP32: liveins: $f12, $f14
141    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
142    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
143    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
144    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
145    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
146    ; FP32: $v0 = COPY [[MOVT_I]]
147    ; FP32: RetRA implicit $v0
148    ; FP64-LABEL: name: ord_s
149    ; FP64: liveins: $f12, $f14
150    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
151    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
152    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
153    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
154    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
155    ; FP64: $v0 = COPY [[MOVT_I]]
156    ; FP64: RetRA implicit $v0
157    %0:fprb(s32) = COPY $f12
158    %1:fprb(s32) = COPY $f14
159    %4:gprb(s32) = G_FCMP floatpred(ord), %0(s32), %1
160    %3:gprb(s32) = COPY %4(s32)
161    $v0 = COPY %3(s32)
162    RetRA implicit $v0
163
164...
165---
166name:            oeq_s
167alignment:       4
168legalized:       true
169regBankSelected: true
170tracksRegLiveness: true
171body:             |
172  bb.1.entry:
173    liveins: $f12, $f14
174
175    ; FP32-LABEL: name: oeq_s
176    ; FP32: liveins: $f12, $f14
177    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
178    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
179    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
180    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
181    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
182    ; FP32: $v0 = COPY [[MOVF_I]]
183    ; FP32: RetRA implicit $v0
184    ; FP64-LABEL: name: oeq_s
185    ; FP64: liveins: $f12, $f14
186    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
187    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
188    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
189    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
190    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
191    ; FP64: $v0 = COPY [[MOVF_I]]
192    ; FP64: RetRA implicit $v0
193    %0:fprb(s32) = COPY $f12
194    %1:fprb(s32) = COPY $f14
195    %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s32), %1
196    %3:gprb(s32) = COPY %4(s32)
197    $v0 = COPY %3(s32)
198    RetRA implicit $v0
199
200...
201---
202name:            une_s
203alignment:       4
204legalized:       true
205regBankSelected: true
206tracksRegLiveness: true
207body:             |
208  bb.1.entry:
209    liveins: $f12, $f14
210
211    ; FP32-LABEL: name: une_s
212    ; FP32: liveins: $f12, $f14
213    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
214    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
215    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
216    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
217    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
218    ; FP32: $v0 = COPY [[MOVT_I]]
219    ; FP32: RetRA implicit $v0
220    ; FP64-LABEL: name: une_s
221    ; FP64: liveins: $f12, $f14
222    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
223    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
224    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
225    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
226    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
227    ; FP64: $v0 = COPY [[MOVT_I]]
228    ; FP64: RetRA implicit $v0
229    %0:fprb(s32) = COPY $f12
230    %1:fprb(s32) = COPY $f14
231    %4:gprb(s32) = G_FCMP floatpred(une), %0(s32), %1
232    %3:gprb(s32) = COPY %4(s32)
233    $v0 = COPY %3(s32)
234    RetRA implicit $v0
235
236...
237---
238name:            ueq_s
239alignment:       4
240legalized:       true
241regBankSelected: true
242tracksRegLiveness: true
243body:             |
244  bb.1.entry:
245    liveins: $f12, $f14
246
247    ; FP32-LABEL: name: ueq_s
248    ; FP32: liveins: $f12, $f14
249    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
250    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
251    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
252    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
253    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
254    ; FP32: $v0 = COPY [[MOVF_I]]
255    ; FP32: RetRA implicit $v0
256    ; FP64-LABEL: name: ueq_s
257    ; FP64: liveins: $f12, $f14
258    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
259    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
260    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
261    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
262    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
263    ; FP64: $v0 = COPY [[MOVF_I]]
264    ; FP64: RetRA implicit $v0
265    %0:fprb(s32) = COPY $f12
266    %1:fprb(s32) = COPY $f14
267    %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s32), %1
268    %3:gprb(s32) = COPY %4(s32)
269    $v0 = COPY %3(s32)
270    RetRA implicit $v0
271
272...
273---
274name:            one_s
275alignment:       4
276legalized:       true
277regBankSelected: true
278tracksRegLiveness: true
279body:             |
280  bb.1.entry:
281    liveins: $f12, $f14
282
283    ; FP32-LABEL: name: one_s
284    ; FP32: liveins: $f12, $f14
285    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
286    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
287    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
288    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
289    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
290    ; FP32: $v0 = COPY [[MOVT_I]]
291    ; FP32: RetRA implicit $v0
292    ; FP64-LABEL: name: one_s
293    ; FP64: liveins: $f12, $f14
294    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
295    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
296    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
297    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
298    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
299    ; FP64: $v0 = COPY [[MOVT_I]]
300    ; FP64: RetRA implicit $v0
301    %0:fprb(s32) = COPY $f12
302    %1:fprb(s32) = COPY $f14
303    %4:gprb(s32) = G_FCMP floatpred(one), %0(s32), %1
304    %3:gprb(s32) = COPY %4(s32)
305    $v0 = COPY %3(s32)
306    RetRA implicit $v0
307
308...
309---
310name:            olt_s
311alignment:       4
312legalized:       true
313regBankSelected: true
314tracksRegLiveness: true
315body:             |
316  bb.1.entry:
317    liveins: $f12, $f14
318
319    ; FP32-LABEL: name: olt_s
320    ; FP32: liveins: $f12, $f14
321    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
322    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
323    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
324    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
325    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
326    ; FP32: $v0 = COPY [[MOVF_I]]
327    ; FP32: RetRA implicit $v0
328    ; FP64-LABEL: name: olt_s
329    ; FP64: liveins: $f12, $f14
330    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
331    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
332    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
333    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
334    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
335    ; FP64: $v0 = COPY [[MOVF_I]]
336    ; FP64: RetRA implicit $v0
337    %0:fprb(s32) = COPY $f12
338    %1:fprb(s32) = COPY $f14
339    %4:gprb(s32) = G_FCMP floatpred(olt), %0(s32), %1
340    %3:gprb(s32) = COPY %4(s32)
341    $v0 = COPY %3(s32)
342    RetRA implicit $v0
343
344...
345---
346name:            uge_s
347alignment:       4
348legalized:       true
349regBankSelected: true
350tracksRegLiveness: true
351body:             |
352  bb.1.entry:
353    liveins: $f12, $f14
354
355    ; FP32-LABEL: name: uge_s
356    ; FP32: liveins: $f12, $f14
357    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
358    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
359    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
360    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
361    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
362    ; FP32: $v0 = COPY [[MOVT_I]]
363    ; FP32: RetRA implicit $v0
364    ; FP64-LABEL: name: uge_s
365    ; FP64: liveins: $f12, $f14
366    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
367    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
368    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
369    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
370    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
371    ; FP64: $v0 = COPY [[MOVT_I]]
372    ; FP64: RetRA implicit $v0
373    %0:fprb(s32) = COPY $f12
374    %1:fprb(s32) = COPY $f14
375    %4:gprb(s32) = G_FCMP floatpred(uge), %0(s32), %1
376    %3:gprb(s32) = COPY %4(s32)
377    $v0 = COPY %3(s32)
378    RetRA implicit $v0
379
380...
381---
382name:            ult_s
383alignment:       4
384legalized:       true
385regBankSelected: true
386tracksRegLiveness: true
387body:             |
388  bb.1.entry:
389    liveins: $f12, $f14
390
391    ; FP32-LABEL: name: ult_s
392    ; FP32: liveins: $f12, $f14
393    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
394    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
395    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
396    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
397    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
398    ; FP32: $v0 = COPY [[MOVF_I]]
399    ; FP32: RetRA implicit $v0
400    ; FP64-LABEL: name: ult_s
401    ; FP64: liveins: $f12, $f14
402    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
403    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
404    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
405    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
406    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
407    ; FP64: $v0 = COPY [[MOVF_I]]
408    ; FP64: RetRA implicit $v0
409    %0:fprb(s32) = COPY $f12
410    %1:fprb(s32) = COPY $f14
411    %4:gprb(s32) = G_FCMP floatpred(ult), %0(s32), %1
412    %3:gprb(s32) = COPY %4(s32)
413    $v0 = COPY %3(s32)
414    RetRA implicit $v0
415
416...
417---
418name:            oge_s
419alignment:       4
420legalized:       true
421regBankSelected: true
422tracksRegLiveness: true
423body:             |
424  bb.1.entry:
425    liveins: $f12, $f14
426
427    ; FP32-LABEL: name: oge_s
428    ; FP32: liveins: $f12, $f14
429    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
430    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
431    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
432    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
433    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
434    ; FP32: $v0 = COPY [[MOVT_I]]
435    ; FP32: RetRA implicit $v0
436    ; FP64-LABEL: name: oge_s
437    ; FP64: liveins: $f12, $f14
438    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
439    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
440    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
441    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
442    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
443    ; FP64: $v0 = COPY [[MOVT_I]]
444    ; FP64: RetRA implicit $v0
445    %0:fprb(s32) = COPY $f12
446    %1:fprb(s32) = COPY $f14
447    %4:gprb(s32) = G_FCMP floatpred(oge), %0(s32), %1
448    %3:gprb(s32) = COPY %4(s32)
449    $v0 = COPY %3(s32)
450    RetRA implicit $v0
451
452...
453---
454name:            ole_s
455alignment:       4
456legalized:       true
457regBankSelected: true
458tracksRegLiveness: true
459body:             |
460  bb.1.entry:
461    liveins: $f12, $f14
462
463    ; FP32-LABEL: name: ole_s
464    ; FP32: liveins: $f12, $f14
465    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
466    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
467    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
468    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
469    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
470    ; FP32: $v0 = COPY [[MOVF_I]]
471    ; FP32: RetRA implicit $v0
472    ; FP64-LABEL: name: ole_s
473    ; FP64: liveins: $f12, $f14
474    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
475    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
476    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
477    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
478    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
479    ; FP64: $v0 = COPY [[MOVF_I]]
480    ; FP64: RetRA implicit $v0
481    %0:fprb(s32) = COPY $f12
482    %1:fprb(s32) = COPY $f14
483    %4:gprb(s32) = G_FCMP floatpred(ole), %0(s32), %1
484    %3:gprb(s32) = COPY %4(s32)
485    $v0 = COPY %3(s32)
486    RetRA implicit $v0
487
488...
489---
490name:            ugt_s
491alignment:       4
492legalized:       true
493regBankSelected: true
494tracksRegLiveness: true
495body:             |
496  bb.1.entry:
497    liveins: $f12, $f14
498
499    ; FP32-LABEL: name: ugt_s
500    ; FP32: liveins: $f12, $f14
501    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
502    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
503    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
504    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
505    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
506    ; FP32: $v0 = COPY [[MOVT_I]]
507    ; FP32: RetRA implicit $v0
508    ; FP64-LABEL: name: ugt_s
509    ; FP64: liveins: $f12, $f14
510    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
511    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
512    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
513    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
514    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
515    ; FP64: $v0 = COPY [[MOVT_I]]
516    ; FP64: RetRA implicit $v0
517    %0:fprb(s32) = COPY $f12
518    %1:fprb(s32) = COPY $f14
519    %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s32), %1
520    %3:gprb(s32) = COPY %4(s32)
521    $v0 = COPY %3(s32)
522    RetRA implicit $v0
523
524...
525---
526name:            ule_s
527alignment:       4
528legalized:       true
529regBankSelected: true
530tracksRegLiveness: true
531body:             |
532  bb.1.entry:
533    liveins: $f12, $f14
534
535    ; FP32-LABEL: name: ule_s
536    ; FP32: liveins: $f12, $f14
537    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
538    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
539    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
540    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
541    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
542    ; FP32: $v0 = COPY [[MOVF_I]]
543    ; FP32: RetRA implicit $v0
544    ; FP64-LABEL: name: ule_s
545    ; FP64: liveins: $f12, $f14
546    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
547    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
548    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
549    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
550    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
551    ; FP64: $v0 = COPY [[MOVF_I]]
552    ; FP64: RetRA implicit $v0
553    %0:fprb(s32) = COPY $f12
554    %1:fprb(s32) = COPY $f14
555    %4:gprb(s32) = G_FCMP floatpred(ule), %0(s32), %1
556    %3:gprb(s32) = COPY %4(s32)
557    $v0 = COPY %3(s32)
558    RetRA implicit $v0
559
560...
561---
562name:            ogt_s
563alignment:       4
564legalized:       true
565regBankSelected: true
566tracksRegLiveness: true
567body:             |
568  bb.1.entry:
569    liveins: $f12, $f14
570
571    ; FP32-LABEL: name: ogt_s
572    ; FP32: liveins: $f12, $f14
573    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
574    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
575    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
576    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
577    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
578    ; FP32: $v0 = COPY [[MOVT_I]]
579    ; FP32: RetRA implicit $v0
580    ; FP64-LABEL: name: ogt_s
581    ; FP64: liveins: $f12, $f14
582    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
583    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
584    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
585    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
586    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
587    ; FP64: $v0 = COPY [[MOVT_I]]
588    ; FP64: RetRA implicit $v0
589    %0:fprb(s32) = COPY $f12
590    %1:fprb(s32) = COPY $f14
591    %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s32), %1
592    %3:gprb(s32) = COPY %4(s32)
593    $v0 = COPY %3(s32)
594    RetRA implicit $v0
595
596...
597---
598name:            false_d
599alignment:       4
600legalized:       true
601regBankSelected: true
602tracksRegLiveness: true
603body:             |
604  bb.1.entry:
605    liveins: $d6, $d7
606
607    ; FP32-LABEL: name: false_d
608    ; FP32: liveins: $d6, $d7
609    ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
610    ; FP32: $v0 = COPY [[ORi]]
611    ; FP32: RetRA implicit $v0
612    ; FP64-LABEL: name: false_d
613    ; FP64: liveins: $d6, $d7
614    ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
615    ; FP64: $v0 = COPY [[ORi]]
616    ; FP64: RetRA implicit $v0
617    %5:gprb(s32) = G_CONSTANT i32 0
618    %4:gprb(s32) = COPY %5(s32)
619    $v0 = COPY %4(s32)
620    RetRA implicit $v0
621
622...
623---
624name:            true_d
625alignment:       4
626legalized:       true
627regBankSelected: true
628tracksRegLiveness: true
629body:             |
630  bb.1.entry:
631    liveins: $d6, $d7
632
633    ; FP32-LABEL: name: true_d
634    ; FP32: liveins: $d6, $d7
635    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
636    ; FP32: $v0 = COPY [[ADDiu]]
637    ; FP32: RetRA implicit $v0
638    ; FP64-LABEL: name: true_d
639    ; FP64: liveins: $d6, $d7
640    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
641    ; FP64: $v0 = COPY [[ADDiu]]
642    ; FP64: RetRA implicit $v0
643    %5:gprb(s32) = G_CONSTANT i32 -1
644    %4:gprb(s32) = COPY %5(s32)
645    $v0 = COPY %4(s32)
646    RetRA implicit $v0
647
648...
649---
650name:            uno_d
651alignment:       4
652legalized:       true
653regBankSelected: true
654tracksRegLiveness: true
655body:             |
656  bb.1.entry:
657    liveins: $d6, $d7
658
659    ; FP32-LABEL: name: uno_d
660    ; FP32: liveins: $d6, $d7
661    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
662    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
663    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
664    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
665    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
666    ; FP32: $v0 = COPY [[MOVF_I]]
667    ; FP32: RetRA implicit $v0
668    ; FP64-LABEL: name: uno_d
669    ; FP64: liveins: $d6, $d7
670    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
671    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
672    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
673    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
674    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
675    ; FP64: $v0 = COPY [[MOVF_I]]
676    ; FP64: RetRA implicit $v0
677    %0:fprb(s64) = COPY $d6
678    %1:fprb(s64) = COPY $d7
679    %4:gprb(s32) = G_FCMP floatpred(uno), %0(s64), %1
680    %3:gprb(s32) = COPY %4(s32)
681    $v0 = COPY %3(s32)
682    RetRA implicit $v0
683
684...
685---
686name:            ord_d
687alignment:       4
688legalized:       true
689regBankSelected: true
690tracksRegLiveness: true
691body:             |
692  bb.1.entry:
693    liveins: $d6, $d7
694
695    ; FP32-LABEL: name: ord_d
696    ; FP32: liveins: $d6, $d7
697    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
698    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
699    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
700    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
701    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
702    ; FP32: $v0 = COPY [[MOVT_I]]
703    ; FP32: RetRA implicit $v0
704    ; FP64-LABEL: name: ord_d
705    ; FP64: liveins: $d6, $d7
706    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
707    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
708    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
709    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
710    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
711    ; FP64: $v0 = COPY [[MOVT_I]]
712    ; FP64: RetRA implicit $v0
713    %0:fprb(s64) = COPY $d6
714    %1:fprb(s64) = COPY $d7
715    %4:gprb(s32) = G_FCMP floatpred(ord), %0(s64), %1
716    %3:gprb(s32) = COPY %4(s32)
717    $v0 = COPY %3(s32)
718    RetRA implicit $v0
719
720...
721---
722name:            oeq_d
723alignment:       4
724legalized:       true
725regBankSelected: true
726tracksRegLiveness: true
727body:             |
728  bb.1.entry:
729    liveins: $d6, $d7
730
731    ; FP32-LABEL: name: oeq_d
732    ; FP32: liveins: $d6, $d7
733    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
734    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
735    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
736    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
737    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
738    ; FP32: $v0 = COPY [[MOVF_I]]
739    ; FP32: RetRA implicit $v0
740    ; FP64-LABEL: name: oeq_d
741    ; FP64: liveins: $d6, $d7
742    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
743    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
744    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
745    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
746    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
747    ; FP64: $v0 = COPY [[MOVF_I]]
748    ; FP64: RetRA implicit $v0
749    %0:fprb(s64) = COPY $d6
750    %1:fprb(s64) = COPY $d7
751    %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s64), %1
752    %3:gprb(s32) = COPY %4(s32)
753    $v0 = COPY %3(s32)
754    RetRA implicit $v0
755
756...
757---
758name:            une_d
759alignment:       4
760legalized:       true
761regBankSelected: true
762tracksRegLiveness: true
763body:             |
764  bb.1.entry:
765    liveins: $d6, $d7
766
767    ; FP32-LABEL: name: une_d
768    ; FP32: liveins: $d6, $d7
769    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
770    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
771    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
772    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
773    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
774    ; FP32: $v0 = COPY [[MOVT_I]]
775    ; FP32: RetRA implicit $v0
776    ; FP64-LABEL: name: une_d
777    ; FP64: liveins: $d6, $d7
778    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
779    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
780    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
781    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
782    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
783    ; FP64: $v0 = COPY [[MOVT_I]]
784    ; FP64: RetRA implicit $v0
785    %0:fprb(s64) = COPY $d6
786    %1:fprb(s64) = COPY $d7
787    %4:gprb(s32) = G_FCMP floatpred(une), %0(s64), %1
788    %3:gprb(s32) = COPY %4(s32)
789    $v0 = COPY %3(s32)
790    RetRA implicit $v0
791
792...
793---
794name:            ueq_d
795alignment:       4
796legalized:       true
797regBankSelected: true
798tracksRegLiveness: true
799body:             |
800  bb.1.entry:
801    liveins: $d6, $d7
802
803    ; FP32-LABEL: name: ueq_d
804    ; FP32: liveins: $d6, $d7
805    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
806    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
807    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
808    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
809    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
810    ; FP32: $v0 = COPY [[MOVF_I]]
811    ; FP32: RetRA implicit $v0
812    ; FP64-LABEL: name: ueq_d
813    ; FP64: liveins: $d6, $d7
814    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
815    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
816    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
817    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
818    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
819    ; FP64: $v0 = COPY [[MOVF_I]]
820    ; FP64: RetRA implicit $v0
821    %0:fprb(s64) = COPY $d6
822    %1:fprb(s64) = COPY $d7
823    %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s64), %1
824    %3:gprb(s32) = COPY %4(s32)
825    $v0 = COPY %3(s32)
826    RetRA implicit $v0
827
828...
829---
830name:            one_d
831alignment:       4
832legalized:       true
833regBankSelected: true
834tracksRegLiveness: true
835body:             |
836  bb.1.entry:
837    liveins: $d6, $d7
838
839    ; FP32-LABEL: name: one_d
840    ; FP32: liveins: $d6, $d7
841    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
842    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
843    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
844    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
845    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
846    ; FP32: $v0 = COPY [[MOVT_I]]
847    ; FP32: RetRA implicit $v0
848    ; FP64-LABEL: name: one_d
849    ; FP64: liveins: $d6, $d7
850    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
851    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
852    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
853    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
854    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
855    ; FP64: $v0 = COPY [[MOVT_I]]
856    ; FP64: RetRA implicit $v0
857    %0:fprb(s64) = COPY $d6
858    %1:fprb(s64) = COPY $d7
859    %4:gprb(s32) = G_FCMP floatpred(one), %0(s64), %1
860    %3:gprb(s32) = COPY %4(s32)
861    $v0 = COPY %3(s32)
862    RetRA implicit $v0
863
864...
865---
866name:            olt_d
867alignment:       4
868legalized:       true
869regBankSelected: true
870tracksRegLiveness: true
871body:             |
872  bb.1.entry:
873    liveins: $d6, $d7
874
875    ; FP32-LABEL: name: olt_d
876    ; FP32: liveins: $d6, $d7
877    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
878    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
879    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
880    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
881    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
882    ; FP32: $v0 = COPY [[MOVF_I]]
883    ; FP32: RetRA implicit $v0
884    ; FP64-LABEL: name: olt_d
885    ; FP64: liveins: $d6, $d7
886    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
887    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
888    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
889    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
890    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
891    ; FP64: $v0 = COPY [[MOVF_I]]
892    ; FP64: RetRA implicit $v0
893    %0:fprb(s64) = COPY $d6
894    %1:fprb(s64) = COPY $d7
895    %4:gprb(s32) = G_FCMP floatpred(olt), %0(s64), %1
896    %3:gprb(s32) = COPY %4(s32)
897    $v0 = COPY %3(s32)
898    RetRA implicit $v0
899
900...
901---
902name:            uge_d
903alignment:       4
904legalized:       true
905regBankSelected: true
906tracksRegLiveness: true
907body:             |
908  bb.1.entry:
909    liveins: $d6, $d7
910
911    ; FP32-LABEL: name: uge_d
912    ; FP32: liveins: $d6, $d7
913    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
914    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
915    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
916    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
917    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
918    ; FP32: $v0 = COPY [[MOVT_I]]
919    ; FP32: RetRA implicit $v0
920    ; FP64-LABEL: name: uge_d
921    ; FP64: liveins: $d6, $d7
922    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
923    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
924    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
925    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
926    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
927    ; FP64: $v0 = COPY [[MOVT_I]]
928    ; FP64: RetRA implicit $v0
929    %0:fprb(s64) = COPY $d6
930    %1:fprb(s64) = COPY $d7
931    %4:gprb(s32) = G_FCMP floatpred(uge), %0(s64), %1
932    %3:gprb(s32) = COPY %4(s32)
933    $v0 = COPY %3(s32)
934    RetRA implicit $v0
935
936...
937---
938name:            ult_d
939alignment:       4
940legalized:       true
941regBankSelected: true
942tracksRegLiveness: true
943body:             |
944  bb.1.entry:
945    liveins: $d6, $d7
946
947    ; FP32-LABEL: name: ult_d
948    ; FP32: liveins: $d6, $d7
949    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
950    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
951    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
952    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
953    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
954    ; FP32: $v0 = COPY [[MOVF_I]]
955    ; FP32: RetRA implicit $v0
956    ; FP64-LABEL: name: ult_d
957    ; FP64: liveins: $d6, $d7
958    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
959    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
960    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
961    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
962    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
963    ; FP64: $v0 = COPY [[MOVF_I]]
964    ; FP64: RetRA implicit $v0
965    %0:fprb(s64) = COPY $d6
966    %1:fprb(s64) = COPY $d7
967    %4:gprb(s32) = G_FCMP floatpred(ult), %0(s64), %1
968    %3:gprb(s32) = COPY %4(s32)
969    $v0 = COPY %3(s32)
970    RetRA implicit $v0
971
972...
973---
974name:            oge_d
975alignment:       4
976legalized:       true
977regBankSelected: true
978tracksRegLiveness: true
979body:             |
980  bb.1.entry:
981    liveins: $d6, $d7
982
983    ; FP32-LABEL: name: oge_d
984    ; FP32: liveins: $d6, $d7
985    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
986    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
987    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
988    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
989    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
990    ; FP32: $v0 = COPY [[MOVT_I]]
991    ; FP32: RetRA implicit $v0
992    ; FP64-LABEL: name: oge_d
993    ; FP64: liveins: $d6, $d7
994    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
995    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
996    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
997    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
998    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
999    ; FP64: $v0 = COPY [[MOVT_I]]
1000    ; FP64: RetRA implicit $v0
1001    %0:fprb(s64) = COPY $d6
1002    %1:fprb(s64) = COPY $d7
1003    %4:gprb(s32) = G_FCMP floatpred(oge), %0(s64), %1
1004    %3:gprb(s32) = COPY %4(s32)
1005    $v0 = COPY %3(s32)
1006    RetRA implicit $v0
1007
1008...
1009---
1010name:            ole_d
1011alignment:       4
1012legalized:       true
1013regBankSelected: true
1014tracksRegLiveness: true
1015body:             |
1016  bb.1.entry:
1017    liveins: $d6, $d7
1018
1019    ; FP32-LABEL: name: ole_d
1020    ; FP32: liveins: $d6, $d7
1021    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
1022    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
1023    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
1024    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
1025    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
1026    ; FP32: $v0 = COPY [[MOVF_I]]
1027    ; FP32: RetRA implicit $v0
1028    ; FP64-LABEL: name: ole_d
1029    ; FP64: liveins: $d6, $d7
1030    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
1031    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
1032    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
1033    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
1034    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
1035    ; FP64: $v0 = COPY [[MOVF_I]]
1036    ; FP64: RetRA implicit $v0
1037    %0:fprb(s64) = COPY $d6
1038    %1:fprb(s64) = COPY $d7
1039    %4:gprb(s32) = G_FCMP floatpred(ole), %0(s64), %1
1040    %3:gprb(s32) = COPY %4(s32)
1041    $v0 = COPY %3(s32)
1042    RetRA implicit $v0
1043
1044...
1045---
1046name:            ugt_d
1047alignment:       4
1048legalized:       true
1049regBankSelected: true
1050tracksRegLiveness: true
1051body:             |
1052  bb.1.entry:
1053    liveins: $d6, $d7
1054
1055    ; FP32-LABEL: name: ugt_d
1056    ; FP32: liveins: $d6, $d7
1057    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
1058    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
1059    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
1060    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
1061    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
1062    ; FP32: $v0 = COPY [[MOVT_I]]
1063    ; FP32: RetRA implicit $v0
1064    ; FP64-LABEL: name: ugt_d
1065    ; FP64: liveins: $d6, $d7
1066    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
1067    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
1068    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
1069    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
1070    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
1071    ; FP64: $v0 = COPY [[MOVT_I]]
1072    ; FP64: RetRA implicit $v0
1073    %0:fprb(s64) = COPY $d6
1074    %1:fprb(s64) = COPY $d7
1075    %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s64), %1
1076    %3:gprb(s32) = COPY %4(s32)
1077    $v0 = COPY %3(s32)
1078    RetRA implicit $v0
1079
1080...
1081---
1082name:            ule_d
1083alignment:       4
1084legalized:       true
1085regBankSelected: true
1086tracksRegLiveness: true
1087body:             |
1088  bb.1.entry:
1089    liveins: $d6, $d7
1090
1091    ; FP32-LABEL: name: ule_d
1092    ; FP32: liveins: $d6, $d7
1093    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
1094    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
1095    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
1096    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
1097    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
1098    ; FP32: $v0 = COPY [[MOVF_I]]
1099    ; FP32: RetRA implicit $v0
1100    ; FP64-LABEL: name: ule_d
1101    ; FP64: liveins: $d6, $d7
1102    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
1103    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
1104    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
1105    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
1106    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
1107    ; FP64: $v0 = COPY [[MOVF_I]]
1108    ; FP64: RetRA implicit $v0
1109    %0:fprb(s64) = COPY $d6
1110    %1:fprb(s64) = COPY $d7
1111    %4:gprb(s32) = G_FCMP floatpred(ule), %0(s64), %1
1112    %3:gprb(s32) = COPY %4(s32)
1113    $v0 = COPY %3(s32)
1114    RetRA implicit $v0
1115
1116...
1117---
1118name:            ogt_d
1119alignment:       4
1120legalized:       true
1121regBankSelected: true
1122tracksRegLiveness: true
1123body:             |
1124  bb.1.entry:
1125    liveins: $d6, $d7
1126
1127    ; FP32-LABEL: name: ogt_d
1128    ; FP32: liveins: $d6, $d7
1129    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
1130    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
1131    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
1132    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
1133    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
1134    ; FP32: $v0 = COPY [[MOVT_I]]
1135    ; FP32: RetRA implicit $v0
1136    ; FP64-LABEL: name: ogt_d
1137    ; FP64: liveins: $d6, $d7
1138    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
1139    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
1140    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
1141    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
1142    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
1143    ; FP64: $v0 = COPY [[MOVT_I]]
1144    ; FP64: RetRA implicit $v0
1145    %0:fprb(s64) = COPY $d6
1146    %1:fprb(s64) = COPY $d7
1147    %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s64), %1
1148    %3:gprb(s32) = COPY %4(s32)
1149    $v0 = COPY %3(s32)
1150    RetRA implicit $v0
1151
1152...
1153