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/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dfcmp.mir605 liveins: $d6, $d7
608 ; FP32: liveins: $d6, $d7
613 ; FP64: liveins: $d6, $d7
631 liveins: $d6, $d7
634 ; FP32: liveins: $d6, $d7
639 ; FP64: liveins: $d6, $d7
657 liveins: $d6, $d7
660 ; FP32: liveins: $d6, $d7
661 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
669 ; FP64: liveins: $d6, $d7
[all …]
H A Dfloat_arithmetic_operations.mir148 liveins: $d6, $d7
151 ; FP32: liveins: $d6, $d7
152 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
158 ; FP64: liveins: $d6, $d7
159 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
164 %0:fprb(s64) = COPY $d6
179 liveins: $d6, $d7
182 ; FP32: liveins: $d6, $d7
183 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
189 ; FP64: liveins: $d6, $d7
[all …]
H A Dfsqrt.mir46 liveins: $d6
49 ; FP32: liveins: $d6
50 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
55 ; FP64: liveins: $d6
56 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
60 %0:fprb(s64) = COPY $d6
H A Dfabs.mir46 liveins: $d6
49 ; FP32: liveins: $d6
50 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
55 ; FP64: liveins: $d6
56 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
60 %0:fprb(s64) = COPY $d6
H A Dfloat_args.mir49 liveins: $d6, $d7
52 ; FP32: liveins: $d6, $d7
57 ; FP64: liveins: $d6, $d7
176 liveins: $d6, $d7
179 ; FP32: liveins: $d6, $d7
180 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
183 ; FP32: $d6 = COPY [[COPY]]
185 …; FP32: JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d…
191 ; FP64: liveins: $d6, $d7
192 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
[all …]
H A Dfpext_and_fptrunc.mir46 liveins: $d6
49 ; FP32: liveins: $d6
50 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
55 ; FP64: liveins: $d6
56 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
60 %0:fprb(s64) = COPY $d6
/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfloat_arithmetic_operations.mir139 liveins: $d6, $d7
142 ; FP32: liveins: $d6, $d7
143 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
149 ; FP64: liveins: $d6, $d7
150 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
155 %0:_(s64) = COPY $d6
168 liveins: $d6, $d7
171 ; FP32: liveins: $d6, $d7
172 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
178 ; FP64: liveins: $d6, $d7
[all …]
H A Dceil_and_floor.mir52 liveins: $d6
55 ; FP32: liveins: $d6
56 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
58 ; FP32: $d6 = COPY [[COPY]](s64)
59 ; FP32: JAL &ceil, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $d0
65 ; FP64: liveins: $d6
66 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
74 %0:_(s64) = COPY $d6
120 liveins: $d6
123 ; FP32: liveins: $d6
[all …]
H A Dfptosi_and_fptoui.mir174 liveins: $d6
177 ; FP32: liveins: $d6
179 ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
181 ; FP32-NEXT: $d6 = COPY [[COPY]](s64)
182 …; FP32-NEXT: JAL &__fixdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-d…
191 ; FP64: liveins: $d6
193 ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
203 %0:_(s64) = COPY $d6
217 liveins: $d6
220 ; FP32: liveins: $d6
[all …]
H A Dfsqrt.mir42 liveins: $d6
45 ; FP32: liveins: $d6
46 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
51 ; FP64: liveins: $d6
52 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
56 %0:_(s64) = COPY $d6
H A Dfabs.mir42 liveins: $d6
45 ; FP32: liveins: $d6
46 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
51 ; FP64: liveins: $d6
52 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
56 %0:_(s64) = COPY $d6
H A Dfpext_and_fptrunc.mir42 liveins: $d6
45 ; FP32: liveins: $d6
46 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
51 ; FP64: liveins: $d6
52 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
56 %0:_(s64) = COPY $d6
/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir144 liveins: $d6, $d7
147 ; FP32: liveins: $d6, $d7
148 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
154 ; FP64: liveins: $d6, $d7
155 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
160 %0:_(s64) = COPY $d6
174 liveins: $d6, $d7
177 ; FP32: liveins: $d6, $d7
178 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
184 ; FP64: liveins: $d6, $d7
[all …]
H A Dfptosi_and_fptoui.mir44 liveins: $d6
47 ; FP32: liveins: $d6
48 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
53 ; FP64: liveins: $d6
54 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
58 %0:_(s64) = COPY $d6
H A Dfsqrt.mir44 liveins: $d6
47 ; FP32: liveins: $d6
48 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
53 ; FP64: liveins: $d6
54 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
58 %0:_(s64) = COPY $d6
H A Dfabs.mir44 liveins: $d6
47 ; FP32: liveins: $d6
48 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
53 ; FP64: liveins: $d6
54 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
58 %0:_(s64) = COPY $d6
/llvm-project/llvm/test/MC/ARM/
H A Dsingle-precision-fp.s7 vdiv.f64 d4, d5, d6
8 vmul.f64 d6, d7, d8
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
17 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
22 vmls.f64 d8, d7, d6
26 vfms.f64 d4, d5, d6
32 @ CHECK-ERRORS-NEXT: vmls.f64 d8, d7, d6
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
60 vcmp.f64 d6, #0
70 @ CHECK-ERRORS-NEXT: vcmp.f64 d6, #0
[all …]
H A Dneon-vld-encoding.s12 vld1.16 {d4, d5, d6}, [r3:64]
13 vld1.32 {d5, d6, d7}, [r3]
14 vld1.64 {d6, d7, d8}, [r3:64]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
18 vld1.64 {d6, d7, d8, d9}, [r3:64]
39 vld1.16 {d4, d5, d6}, [r3:64]!
40 vld1.32 {d5, d6, d7}, [r3]!
41 vld1.64 {d6, d7, d8}, [r3:64]!
44 vld1.16 {d4, d5, d6}, [r3:64], r6
[all …]
H A Dneon-vld-vst-align.s4153 vld4.8 {d0, d2, d4, d6}, [r4]
4154 vld4.8 {d0, d2, d4, d6}, [r4:16]
4155 vld4.8 {d0, d2, d4, d6}, [r4:32]
4156 vld4.8 {d0, d2, d4, d6}, [r4:64]
4157 vld4.8 {d0, d2, d4, d6}, [r4:128]
4158 vld4.8 {d0, d2, d4, d6}, [r4:256]
4160 @ CHECK: vld4.8 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x0f,0x01]
4162 @ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16]
4165 @ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32]
4167 @ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x01]
[all …]
/llvm-project/clang/test/CodeGen/
H A Daarch64-ABI-align-packed-assembly.c
/llvm-project/llvm/test/CodeGen/ARM/
H A Dha-alignstack.ll31 …e %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %…
41 …e %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, %struct.S1 alignsta…
51 …e %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, float %x, %struct.S…
61 …e %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %…
91 …e %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %…
107 ; CHECK: vmov.f64 d0, d6
111 …e %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, %struct.D0 %s.coerc…
121 …e %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %…
137 ; CHECK: vmov.f64 d0, d6
141 …e %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, %struct.D1 alignsta…
[all …]
/llvm-project/llvm/test/CodeGen/Mips/longbranch/
H A Dbranch-limits-fp-micromips.mir47 - { reg: '$d6', virtual-reg: '' }
74 ; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
93 ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
121 liveins: $d6, $d7
123 FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
147 - { reg: '$d6', virtual-reg: '' }
174 ; MM: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
188 ; PIC: FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
201 liveins: $d6, $d7
203 FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
/llvm-project/compiler-rt/lib/builtins/arm/
H A Dadddf3vfp.S22 VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
24 vadd.f64 d6, d6, d7
25 VMOV_FROM_DOUBLE(r0, r1, d6) // move result back to r0/r1 pair
H A Dmuldf3vfp.S23 VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
25 vmul.f64 d6, d6, d7
26 VMOV_FROM_DOUBLE(r0, r1, d6) // move result back to r0/r1 pair
H A Dsubdf3vfp.S23 VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
25 vsub.f64 d6, d6, d7
26 VMOV_FROM_DOUBLE(r0, r1, d6) // move result back to r0/r1 pair

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