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/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 number is defined at design time, the maximum of each defined in the DEVID
26 programmable channels, usually 4, but again implementation defined and
32 are implementation defined, except when the CTI is connected to an ARM v8
37 architecturally connected CTI an additional compatible string is used to
38 indicate this feature (arm,coresight-cti-v8-arch).
52 and usages. These can be defined along with the signal indexes with the
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H A Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
21 number is defined at design time, the maximum of each defined in the DEVID
25 programmable channels, usually 4, but again implementation defined and
31 are implementation defined, except when the CTI is connected to an ARM v8
36 architecturally connected CTI an additional compatible string is used to
37 indicate this feature (arm,coresight-cti-v8-arch).
51 and usages. These can be defined along with the signal indexes with the
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/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
27 - compatible : "riscv,cpu-intc"
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/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enu
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H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/MCA/
H A DPipeline.h1 //===--------------------- Pipeline.h ---------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
28 /// It emulates an out-of-order execution of instructions. Instructions are
35 /// executing and register writes are architecturally committed.
40 /// is defined by the SourceMgr object, which is managed by the initial stage
/freebsd-src/lib/libpmc/pmu-events/arch/x86/silvermont/
H A Dpipeline.json108 …architecturally defined event. This event counts the number of retired branch instructions that we…
117 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
127 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
137 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
147 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
157 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
165 …by dividing the event count by the core frequency. This event is architecturally defined and is a …
190 …lapsed time while the core was not in halt state. This event is architecturally defined and is a …
207 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
216 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRetireControlUnit.h1 //===---------------------- RetireControlUnit.h -----------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
25 /// This class tracks which instructions are in-flight (i.e., dispatched but not
33 /// On instruction retired, register updates are all architecturally
42 // flag set, then the instruction has reached the write-back stage and will
49 // Note that the size of the reorder buffer is defined by the scheduling
/freebsd-src/contrib/llvm-project/compiler-rt/lib/scudo/standalone/include/scudo/
H A Dinterface.h1 //===-- scudo/interface.h ---------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
19 // Post-allocation & pre-deallocation hooks.
44 // of reports are zero-initialized.
79 // equal to the architecturally defined memory tag granule size (16 on aarch64).
127 #define M_DECAY_TIME -100
131 #define M_PURGE -101
135 #define M_PURGE_ALL -104
142 #define M_MEMTAG_TUNING -102
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/freebsd-src/sys/amd64/include/
H A Dvmm.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 * Identifiers for architecturally defined registers.
144 (SPECNAMELEN - VM_MAX_PREFIXLEN - VM_MAX_SUFFIXLEN -
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/freebsd-src/sys/arm64/include/
H A Dvmm.h49 * Identifiers for architecturally defined registers.
126 (SPECNAMELEN - VM_MAX_PREFIXLEN - VM_MAX_SUFFIXLEN - 1)
224 return (*((uintptr_t *)(info->rptr)) != 0);
231 return (*info->sptr); in vcpu_is_running()
259 return (td->td_ast != 0 || td->td_owepreempt != 0);
/freebsd-src/sys/arm/arm/
H A Dswtch-v6.S3 /*-
37 /*-
38 * Copyright (c) 1994-1998 Mark Brinicombe.
89 #if defined(SMP)
140 * is not architecturally invisible. See ARM Architecture Reference
141 * Manual ARMv7-A and ARMv7-R edition, page B2-1264(65), Branch
148 * is effectively NOP on Cortex-A15 so it needs special treatment.
154 /* Branch Target Cache on Cortex-A15. */
238 ldr r6, [r11, #(TD_PROC)] /* newtd->proc */
239 ldr r6, [r6, #(P_VMSPACE)] /* newtd->proc->vmspace */
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/freebsd-src/usr.bin/clang/llvm-mca/
H A Dllvm-mca.14 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
19 . nr rst2man-indent-level +1
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/freebsd-src/lib/libpmc/
H A Dpmc.westmere.344 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
114 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
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H A Dpmc.corei7.344 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
5 // SPDX-Licens
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp1 //===- AArch64SpeculationHardening.cpp - Harden Against Missspeculation --===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // vulnerabilities that may happen under control flow miss-speculation.
12 // The pass implements tracking of control flow miss-speculation into a "taint"
14 // sensitive data when executing under miss-speculation, a.k.a. "transient
16 // This pass is aimed at mitigating against SpectreV1-style vulnarabilities.
21 // As a possible follow-on improvement, also an intrinsics-based approach as
26 // tracking of control flow miss-speculation into a taint register:
29 // the instruction set characteristics result in different trade-offs.
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -------
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/freebsd-src/sys/x86/iommu/
H A Dintel_drv.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
32 #if defined(__amd64__)
104 ptrend = (char *)dmartbl + dmartbl->Header.Length; in dmar_iterate_tbl()
109 if (dmarh->Length <= 0) { in dmar_iterate_tbl()
111 dmarh->Lengt in dmar_iterate_tbl()
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/freebsd-src/sys/arm64/vmm/io/
H A Dvgic_v3.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (C) 2020-2022 Andrew Turner
79 #define VGIC_SGI_NUM (GIC_LAST_SGI - GIC_FIRST_SGI + 1)
80 #define VGIC_PPI_NUM (GIC_LAST_PPI - GIC_FIRST_PPI + 1)
81 #define VGIC_SPI_NUM (GIC_LAST_SPI - GIC_FIRST_SPI + 1)
127 /* Per-CP
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/freebsd-src/sys/arm64/arm64/
H A Didentcpu.c1 /*-
88 * The default implementation of I-cache sync assumes we have an
103 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) in sysctl_hw_machine()
120 architecturally. */
122 * Per-CPU affinity as provided in MPIDR_EL1
128 * Aff1 - Cluster number
129 * Aff0 - CPU number in Aff1 cluster
177 return (&cpu_desc[cpu - 1]);
190 * Part number is implementation defined
198 * Per-implemente
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/freebsd-src/contrib/llvm-project/clang/lib/Headers/
H A Daltivec.h1 /*===---- altivec.h - Standard header for type generic math ---------------===*\
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 \*===----------------------------------------------------------------------===*/
118 return __builtin_altivec_vmaxsb(__a, -__a); in vec_abs()
123 return __builtin_altivec_vmaxsh(__a, -__a); in vec_abs()
128 return __builtin_altivec_vmaxsw(__a, -__a); in vec_abs()
134 return __builtin_altivec_vmaxsd(__a, -__a); in vec_abs()
178 #if defined(__POWER9_VECTOR__)
316 #elif defined(__VSX__)
614 #endif // defined(__POWER8_VECTOR__) && defined(__powerpc64__)
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
5 // SPDX-License-Identifie
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------
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/freebsd-src/share/dict/
H A Dweb212715 architecturally
50006 defined
99810 Jean-Christophe
99811 Jean-Pierre