Lines Matching +full:architecturally +full:- +full:defined
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
32 #if defined(__amd64__)
104 ptrend = (char *)dmartbl + dmartbl->Header.Length;
109 if (dmarh->Length <= 0) {
111 dmarh->Length);
114 ptr += dmarh->Length;
131 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
135 if (fia->i == 0) {
136 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
139 fia->i--;
158 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
175 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_AFFINITY) {
178 if (adr->BaseAddress == ria->base)
179 ria->proxim_dom = adr->ProximityDomain;
206 haw = dmartbl->Width + 1;
212 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
213 (unsigned)dmartbl->Flags,
235 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
239 i, (uintmax_t)dmarh->Address, error);
245 ria.base = dmarh->Address;
246 ria.proxim_dom = -1;
248 acpi_set_domain(dmar_devs[i], ria.proxim_dom == -1 ?
269 iommu_fini_busdma(&unit->iommu);
275 if (unit->regs != NULL) {
276 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
277 unit->regs);
278 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
279 unit->regs);
280 unit->regs = NULL;
282 if (unit->domids != NULL) {
283 delete_unrhdr(unit->domids);
284 unit->domids = NULL;
286 if (unit->ctx_obj != NULL) {
287 vm_object_deallocate(unit->ctx_obj);
288 unit->ctx_obj = NULL;
290 sysctl_ctx_free(&unit->iommu.sysctl_ctx);
305 dmd = &unit->x86c.intrs[i];
306 if (irq == dmd->irq) {
313 dmd->msi_data = msi_data;
314 dmd->msi_addr = msi_addr;
315 (dmd->disable_intr)(DMAR2IOMMU(unit));
316 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
317 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
318 dmar_write4(unit, dmd->msi_uaddr_reg,
319 dmd->msi_addr >> 32);
320 (dmd->enable_intr)(DMAR2IOMMU(unit));
336 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
337 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
338 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
339 caphi = unit->hw_cap >> 32;
340 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
344 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
345 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
346 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
347 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
348 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
350 ecaphi = unit->hw_ecap >> 32;
351 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
355 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
356 DMAR_ECAP_IRO(unit->hw_ecap));
370 unit->iommu.unit = device_get_unit(dev);
371 unit->iommu.dev = dev;
372 sysctl_ctx_init(&unit->iommu.sysctl_ctx);
373 dmaru = dmar_find_by_index(unit->iommu.unit);
376 unit->segment = dmaru->Segment;
377 unit->base = dmaru->Address;
378 unit->reg_rid = DMAR_REG_RID;
379 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
380 &unit->reg_rid, RF_ACTIVE);
381 if (unit->regs == NULL) {
383 dmar_devs[unit->iommu.unit] = NULL;
386 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
387 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
388 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
392 unit->memdomain = acpi_get_domain(dev);
398 unit->x86c.intrs[i].irq = -1;
400 dmd = &unit->x86c.intrs[DMAR_INTR_FAULT];
401 dmd->name = "fault";
402 dmd->irq_rid = DMAR_FAULT_IRQ_RID;
403 dmd->handler = dmar_fault_intr;
404 dmd->msi_data_reg = DMAR_FEDATA_REG;
405 dmd->msi_addr_reg = DMAR_FEADDR_REG;
406 dmd->msi_uaddr_reg = DMAR_FEUADDR_REG;
407 dmd->enable_intr = dmar_enable_fault_intr;
408 dmd->disable_intr = dmar_disable_fault_intr;
412 dmar_devs[unit->iommu.unit] = NULL;
415 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
416 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
417 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32);
420 dmd = &unit->x86c.intrs[DMAR_INTR_QI];
421 dmd->name = "qi";
422 dmd->irq_rid = DMAR_QI_IRQ_RID;
423 dmd->handler = dmar_qi_intr;
424 dmd->msi_data_reg = DMAR_IEDATA_REG;
425 dmd->msi_addr_reg = DMAR_IEADDR_REG;
426 dmd->msi_uaddr_reg = DMAR_IEUADDR_REG;
427 dmd->enable_intr = dmar_enable_qi_intr;
428 dmd->disable_intr = dmar_disable_qi_intr;
432 dmar_devs[unit->iommu.unit] = NULL;
436 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
437 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
438 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32);
441 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF);
442 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
443 &unit->iommu.lock);
444 LIST_INIT(&unit->domains);
449 * domain-id value of zero is architecturally reserved.
450 * Software must not use domain-id value of zero
453 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
454 alloc_unr_specific(unit->domids, 0);
456 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
458 if (unit->memdomain != -1) {
459 unit->ctx_obj->domain.dr_policy = DOMAINSET_PREF(
460 unit->memdomain);
468 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO);
474 dmar_devs[unit->iommu.unit] = NULL;
481 dmar_devs[unit->iommu.unit] = NULL;
484 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
489 dmar_devs[unit->iommu.unit] = NULL;
498 dmar_devs[unit->iommu.unit] = NULL;
504 dmar_devs[unit->iommu.unit] = NULL;
510 dmar_devs[unit->iommu.unit] = NULL;
523 error = iommu_init_busdma(&unit->iommu);
526 dmar_devs[unit->iommu.unit] = NULL;
536 dmar_devs[unit->iommu.unit] = NULL;
630 for (depth--; depth != -1; depth--) {
675 if (devscope->Length < sizeof(*devscope)) {
677 devscope->Length);
678 return (-1);
680 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
681 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
683 path_len = devscope->Length - sizeof(*devscope);
686 devscope->Length);
687 return (-1);
693 devscope->Length);
694 return (-1);
697 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
698 dev_path, dev_path_len, devscope->EntryType));
710 dmarh = dmar_find_by_index(unit->iommu.unit);
713 if (dmarh->Segment != dev_domain)
715 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
721 ptrend = (char *)dmarh + dmarh->Header.Length;
724 ptr += devscope->Length;
727 if (match == -1)
790 pci_get_function(dev), unit->iommu.unit, banner);
795 iommu_device_set_iommu_prop(dev, unit->iommu.dev);
822 ptrend = (char *)dmarh + dmarh->Header.Length;
827 ptr += devscope->Length;
828 if (devscope->EntryType != entry_type)
830 if (devscope->EnumerationId != id)
843 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
848 *rid = PCI_RID(devscope->Bus,
849 path->Device, path->Function);
870 iommu_device_set_iommu_prop(dev, unit->iommu.dev);
884 iommu_device_set_iommu_prop(apic_dev, unit->iommu.dev);
911 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
916 if (resmem->Segment != ria->dev_domain)
920 ptrend = (char *)resmem + resmem->Header.Length;
925 ptr += devscope->Length;
926 match = dmar_match_devscope(devscope, ria->dev_busno,
927 ria->dev_path, ria->dev_path_len);
929 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain),
931 entry->start = resmem->BaseAddress;
933 entry->end = resmem->EndAddress;
934 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
971 dev = pci_find_dbsf(segment, busno, path->Device,
972 path->Function);
973 if (i != path_len - 1) {
974 busno = pci_cfgregread(segment, busno, path->Device,
975 path->Function, PCIR_SECBUS_1, 1);
979 *rid = PCI_RID(busno, path->Device, path->Function);
1000 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
1004 if (resmem->Segment != iria->dmar->segment)
1008 ptrend = (const char *)resmem + resmem->Header.Length;
1013 ptr += devscope->Length;
1015 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
1018 dev_path_len = (devscope->Length -
1020 dev = dmar_path_dev(resmem->Segment, dev_path_len,
1021 devscope->Bus,
1027 iria->dmar->iommu.unit,
1028 (uintmax_t)resmem->BaseAddress,
1029 (uintmax_t)resmem->EndAddress,
1031 dmar_print_path(devscope->Bus, dev_path_len,
1035 unit = dmar_find_by_scope(resmem->Segment,
1036 devscope->Bus,
1039 if (iria->dmar != unit)
1041 dmar_get_ctx_for_devpath(iria->dmar, rid,
1042 resmem->Segment, devscope->Bus,
1047 if (iria->dmar != unit)
1049 iommu_instantiate_ctx(&(iria)->dmar->iommu,
1059 * Pre-create all contexts for the DMAR which have RMRR entries.
1077 if (!LIST_EMPTY(&dmar->domains)) {
1078 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1080 dmar->iommu.unit));
1084 dmar->iommu.unit);
1089 dmar->iommu.unit);
1092 "error %d\n", dmar->iommu.unit, error);
1114 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1115 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt,
1116 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt);
1175 LIST_FOREACH(domain, &unit->domains, link) {
1176 LIST_FOREACH(ctx, &domain->iodom.contexts, link) {
1177 if (pci_domain == unit->segment &&
1178 bus == pci_get_bus(ctx->tag->owner) &&
1179 device == pci_get_slot(ctx->tag->owner) &&
1180 function == pci_get_function(ctx->tag->
1200 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit,
1209 if (unit->ir_enabled) {
1211 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1218 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1219 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1229 if (unit->qi_enabled) {
1234 (uintmax_t)unit->x86c.inv_queue,
1236 (uintmax_t)unit->x86c.inv_queue_size,
1239 unit->x86c.inv_queue_avail,
1242 (uintmax_t)unit->x86c.inv_waitd_seq_hw,
1243 &unit->x86c.inv_waitd_seq_hw,
1244 (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys,
1245 unit->x86c.inv_waitd_seq,
1246 unit->x86c.inv_waitd_gen);
1253 LIST_FOREACH(domain, &unit->domains, link) {
1296 return (&dmar->iommu);
1305 return (&dmar->x86c);