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/llvm-project/llvm/test/Transforms/CorrelatedValuePropagation/
H A Dcrash.ll15 %and.us.us = and i16 %conv6.us.us, %and.us.us
66 %a1 = and i1 %a0, %a0
67 %a2 = and i1 %a1, %a1
68 %a3 = and i1 %a2, %a2
69 %a4 = and i1 %a3, %a3
70 %a5 = and i1 %a4, %a4
71 %a6 = and i1 %a5, %a5
72 %a7 = and i
[all...]
/llvm-project/polly/lib/External/isl/test_inputs/schedule/
H A Dpoliwoda.sc9 domain: [_PB_M, _PB_N] -> { S_0[Id1, Id2, Id3] : _PB_M >= 2 and Id1 >=
10 0 and 4Id1 < _PB_N and 2Id2 >= -_PB_M and 4Id2 <= -_PB_M and Id3 <=
11 0 and 4Id3 >= -3 + _PB_M + 4Id2 and 4Id3 >= -1 - _PB_M; S_1[Id1, Id2,
12 Id3] : _PB_M >= 2 and Id1 >= 0 and 4Id1 < _PB_N and -_PB_M <= 2Id2 <=
13 1 - _PB_M and Id3 <= 0 and 4Id3 >= -1 - _PB_M }
15 Id3'] : Id1 >= 0 and 4Id1 < _PB_N and Id3 <= 0 and 4Id3 >= -3 + _PB_M +
16 4Id2 and Id2' <= Id2 and 2Id2' >= -_PB_M and Id3' < 0 and Id3' <= Id3
17 and Id3' < Id2 + Id3 - Id2' and 4Id3' >= -4 + _PB_M + 4Id2 and 4Id3' >=
18 -3 + _PB_M + 3Id2 + Id2' and -1 - _PB_M <= 4Id3' <= 2 + _PB_M + 4Id2;
19 S_0[Id1, Id2, Id3] -> S_0[Id1' = Id1, Id2', Id3' = Id3] : Id1 >= 0 and
[all …]
/llvm-project/polly/lib/External/isl/test_inputs/codegen/cloog/
H A Dsor1d.st1 …and i4 >= -193 - 200i1 and i4 >= -194 + 100i0 - 200i1 and 100i0 >= -284 - 3N and i4 <= -1 + N and …
3 context: "[M, N] -> { [] : M >= 0 and N >= 0 }"
H A Dmxm-shared.st1 …and g4 = 0 and g2 = 8b0 and 128e0 = g1 and 4096e1 = 128b1 - g1 and 128e2 = -8b0 + g0 and 16e3 = -t…
3 …and g3 = 128b1 and 8e0 = g0 and 4096e1 = -128b1 + g1 and 128e2 = 8b0 - g0 and b0 >= 0 and g4 <= -1…
H A Djacobi-shared.st1 …and 2e0 = -1 + h0 and 2048e1 = -32b0 + g1 and 1024e2 = -32b1 + g2 and 16e3 = -15 - t0 + i0 and 32e…
3 …and 2048e0 = -32b0 + g1 and 1024e1 = -32b1 + g2 and g2 <= -2 + N and g2 >= -29 and g1 <= -2 + N an…
H A Dswim.st1 …and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= Q and i2 >= 1 and i2 <= R; S106[i0, i1, i2] : M = 1 …
H A Dotl.st1 …and innerProcTileIter1 >= outerTimeTileIter - outerProcTileIter2 and 10outerProcTileIter2 >= -2 - …
3 context: "[M, N] -> { [] : M >= 1 and N >= 1 }"
/llvm-project/polly/lib/External/isl/test_inputs/codegen/
H A Droman.in3 …and 4294967296e0 <= np1 - i and 4294967296e0 >= -4294967295 + np1 - i and 4294967296e0 <= np1 - i …
4 … 4294967296e0 <= np1 - i and 4294967296e0 >= -20 + np1 - i and np1 >= -2147483648 and np1 <= 21474…
H A Dshift2.in3 …and 32e0 = o2 and 32e1 = o3 and 32e2 = -length + o5 and 32e3 = -2length + o6 and o2 <= length and …
4 [tsteps, length] -> { : length >= 0 and length <= 1024 and tsteps = 2 }
H A Dredundant.st2 …and o1 >= 0 and o2 <= 12 and o2 >= 1 and o3 <= 14 and o3 >= 1 and 8e0 <= 4 + o2 and 8e1 <= 5 + o2 …
4 context: "[b0] -> { [] : b0 <= 2 and b0 >= 0 }"
H A Dseparate2.in2 …and 32e0 = o2 and 32e1 = o3 and 32e2 = -i + o5 and 32e3 = -31 + j - o6 and o2 <= i and o2 >= -31 +…
3 [tsteps, length] -> { : length >= 1 and length <= 1024 and tsteps = 2 }
/llvm-project/llvm/include/llvm/Support/
H A DX86DisassemblerDecoderCommon.h10 // It contains common definitions used by both the disassembler and the table
91 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
108 "requires a REX.W prefix and 0x67 prefix") \
126 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
127 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
128 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
129 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
130 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
131 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
132 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSiz
[all...]
/llvm-project/flang/test/Evaluate/
H A Dfolding18.f906 .and. ieee_support_datatype(1.0_2) &
7 .and. ieee_support_datatype(1.0_3) &
8 .and. ieee_support_datatype(1.0_4) &
9 .and. ieee_support_datatype(1.0_8) &
10 .and. ieee_support_datatype(1.0_10) &
11 .and. ieee_support_datatype(1.0_16)
13 .and. ieee_support_denormal(1.0_2) &
14 .and. ieee_support_denormal(1.0_3) &
15 .and. ieee_support_denormal(1.0_4) &
16 .and
[all...]
/llvm-project/llvm/test/Transforms/InstSimplify/
H A Dand-icmps-same-ops.ll4 ; There are 10 * 10 combinations of icmp predicates that can be AND'd together.
14 %and = and i1 %cmp1, %cmp2
15 ret i1 %and
24 %and = and i1 %cmp1, %cmp2
25 ret i1 %and
35 %and = and i1 %cmp1, %cmp2
36 ret i1 %and
45 %and = and i1 %cmp1, %cmp2
46 ret i1 %and
56 %and = and i1 %cmp1, %cmp2
[all …]
/llvm-project/llvm/test/Transforms/LoopPredication/
H A Dvisited.ll15 ; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[TMP1]], [[TMP0]]
23 ; CHECK-NEXT: [[GUARD_COND_2:%.*]] = and i1 [[WITHIN_BOUNDS]], [[UNRELATED_COND]]
24 ; CHECK-NEXT: [[GUARD_COND_3:%.*]] = and i1 [[GUARD_COND_2]], [[UNRELATED_COND]]
25 ; CHECK-NEXT: [[GUARD_COND_4:%.*]] = and i1 [[GUARD_COND_3]], [[GUARD_COND_2]]
26 ; CHECK-NEXT: [[GUARD_COND_5:%.*]] = and i1 [[GUARD_COND_4]], [[GUARD_COND_3]]
27 ; CHECK-NEXT: [[GUARD_COND_6:%.*]] = and i1 [[GUARD_COND_5]], [[GUARD_COND_4]]
28 ; CHECK-NEXT: [[GUARD_COND_7:%.*]] = and i1 [[GUARD_COND_6]], [[GUARD_COND_5]]
29 ; CHECK-NEXT: [[GUARD_COND_8:%.*]] = and i1 [[GUARD_COND_7]], [[GUARD_COND_6]]
30 ; CHECK-NEXT: [[GUARD_COND_9:%.*]] = and i1 [[GUARD_COND_8]], [[GUARD_COND_7]]
31 ; CHECK-NEXT: [[GUARD_COND_10:%.*]] = and i1 [[GUARD_COND_9]], [[GUARD_COND_8]]
[all …]
/llvm-project/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-xor.ll12 ; And then into:
21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], [[NEG]]
24 ; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = xor i32 %and, %and1
36 ; CHECK-NEXT: [[AND
[all...]
H A Dmasked-merge-or.ll12 ; And then into:
21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], [[NEG]]
24 ; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = or i32 %and, %and1
36 ; CHECK-NEXT: [[AND
[all...]
H A Dmasked-merge-add.ll12 ; And then into:
21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], [[NEG]]
24 ; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = add i32 %and, %and1
36 ; CHECK-NEXT: [[AND
[all...]
H A Dbit-checks.ll6 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3
11 %and = and i32 %argc, 1
12 %tobool = icmp ne i32 %and, 0
13 %and2 = and i32 %argc, 2
15 %or.cond = and i1 %tobool, %tobool3
22 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3
27 %and = and i32 %argc, 1
28 %tobool = icmp ne i32 %and,
[all...]
/llvm-project/llvm/test/Analysis/ValueTracking/
H A Dknownbits-div.ll11 %and = and i8 %div, 128
12 %r = icmp eq i8 %and, 128
20 %xx = and i8 %x, 127
24 %and = and i8 %div, 128
25 %r = icmp eq i8 %and, 0
31 ; CHECK-NEXT: [[XX:%.*]] = and i8 [[X:%.*]], 127
35 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[DIV]], -128
36 ; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0
39 %xx = and i8 %x, 127
43 %and = and i8 %div, 128
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Drisbg-04.ll14 %and = and i32 %shr, 1
15 ret i32 %and
18 ; ...and again with i64.
25 %and = and i64 %shr, 1
26 ret i64 %and
36 %and = and i32 %shr, 12
37 ret i32 %and
40 ; ...and again with i64.
47 %and = and i64 %shr, 12
48 ret i64 %and
[all …]
H A Drisbg-01.ll16 %and = and i32 %shr, 1
17 ret i32 %and
20 ; ...and again with i64.
27 %and = and i64 %shr, 1
28 ret i64 %and
40 %and = and i32 %shr, 12
41 ret i32 %and
44 ; ...and again with i64.
51 %and = and i64 %shr, 12
52 ret i64 %and
[all …]
H A Drnsbg-01.ll11 %and = and i32 %a, %orb
12 ret i32 %and
15 ; ...and again with i64.
21 %and = and i64 %a, %orb
22 ret i64 %and
31 %and = and i32 %a, %orb
32 ret i32 %and
35 ; ...and again with i64.
41 %and = and i64 %a, %orb
42 ret i64 %and
[all …]
/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
H A Dscalar-cmp-cmp-log-sel.ll11 %and = and i1 %cmp0, %cmp1
12 %sel = select i1 %and, i8 %val5, i8 %val6
18 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
19 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i8 %val5, i8 %val6
26 %and = and i1 %cmp0, %cmp1
27 %sel = select i1 %and, i16 %val5, i16 %val6
33 ; CHECK: cost of 1 for instruction: %and = and i1 %cmp0, %cmp1
34 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i16 %val5, i16 %val6
41 %and = and i1 %cmp0, %cmp1
42 %sel = select i1 %and, i32 %val5, i32 %val6
[all …]
/llvm-project/polly/test/DependenceInfo/
H A Dreduction_sequence.ll62 …and o1 >= 0 and -1024o0 < o1 <= 1023; Stmt_bb90[i0, i1] -> Stmt_bb102[0, 0] : i0 >= 0 and 0 <= i1 …
64 …and o1 >= 0 and -1024o0 < o1 <= 1023; Stmt_bb90[i0, i1] -> Stmt_bb102[0, 0] : i0 >= 0 and 0 <= i1 …
66 …and o1 >= 0 and -1024o0 < o1 <= 1023; Stmt_bb90[i0, i1] -> Stmt_bb102[0, 0] : i0 >= 0 and 0 <= i1 …
68 …and 0 <= i1 <= 1022; Stmt_bb162[i0, 1023] -> Stmt_bb162[1 + i0, 0] : 0 <= i0 <= 1022; Stmt_bb90[i0…
71 …and 0 <= o1 <= 1023 and ((i0 >= 0 and o0 <= 1023 and o1 > 1024i0 + i1 - 1024o0) or (i0 <= 1023 and…

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