1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=instcombine -S | FileCheck %s 3 4define i32 @main1(i32 %argc) { 5; CHECK-LABEL: @main1( 6; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3 7; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 3 8; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 9; CHECK-NEXT: ret i32 [[RETVAL_0]] 10; 11 %and = and i32 %argc, 1 12 %tobool = icmp ne i32 %and, 0 13 %and2 = and i32 %argc, 2 14 %tobool3 = icmp ne i32 %and2, 0 15 %or.cond = and i1 %tobool, %tobool3 16 %retval.0 = select i1 %or.cond, i32 2, i32 1 17 ret i32 %retval.0 18} 19 20define i32 @main1_logical(i32 %argc) { 21; CHECK-LABEL: @main1_logical( 22; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3 23; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 3 24; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 25; CHECK-NEXT: ret i32 [[RETVAL_0]] 26; 27 %and = and i32 %argc, 1 28 %tobool = icmp ne i32 %and, 0 29 %and2 = and i32 %argc, 2 30 %tobool3 = icmp ne i32 %and2, 0 31 %or.cond = select i1 %tobool, i1 %tobool3, i1 false 32 %retval.0 = select i1 %or.cond, i32 2, i32 1 33 ret i32 %retval.0 34} 35 36define i32 @main2(i32 %argc) { 37; CHECK-LABEL: @main2( 38; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3 39; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 3 40; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 41; CHECK-NEXT: ret i32 [[STOREMERGE]] 42; 43 %and = and i32 %argc, 1 44 %tobool = icmp eq i32 %and, 0 45 %and2 = and i32 %argc, 2 46 %tobool3 = icmp eq i32 %and2, 0 47 %or.cond = or i1 %tobool, %tobool3 48 %storemerge = select i1 %or.cond, i32 0, i32 1 49 ret i32 %storemerge 50} 51 52define i32 @main2_logical(i32 %argc) { 53; CHECK-LABEL: @main2_logical( 54; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3 55; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 3 56; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 57; CHECK-NEXT: ret i32 [[STOREMERGE]] 58; 59 %and = and i32 %argc, 1 60 %tobool = icmp eq i32 %and, 0 61 %and2 = and i32 %argc, 2 62 %tobool3 = icmp eq i32 %and2, 0 63 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 64 %storemerge = select i1 %or.cond, i32 0, i32 1 65 ret i32 %storemerge 66} 67 68; tests to check combining (icmp eq (A & B), C) & (icmp eq (A & D), E) 69; tests to check if (icmp eq (A & B), 0) is treated like (icmp eq (A & B), B) 70; if B is a single bit constant 71 72; (icmp eq (A & B), 0) & (icmp eq (A & D), 0) -> (icmp eq (A & (B|D)), 0) 73define i32 @main3(i32 %argc) { 74; CHECK-LABEL: @main3( 75; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 76; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 0 77; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 78; CHECK-NEXT: ret i32 [[STOREMERGE]] 79; 80 %and = and i32 %argc, 7 81 %tobool = icmp eq i32 %and, 0 82 %and2 = and i32 %argc, 48 83 %tobool3 = icmp eq i32 %and2, 0 84 %and.cond = and i1 %tobool, %tobool3 85 %storemerge = select i1 %and.cond, i32 0, i32 1 86 ret i32 %storemerge 87} 88 89define i32 @main3_logical(i32 %argc) { 90; CHECK-LABEL: @main3_logical( 91; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 92; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 0 93; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 94; CHECK-NEXT: ret i32 [[STOREMERGE]] 95; 96 %and = and i32 %argc, 7 97 %tobool = icmp eq i32 %and, 0 98 %and2 = and i32 %argc, 48 99 %tobool3 = icmp eq i32 %and2, 0 100 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 101 %storemerge = select i1 %and.cond, i32 0, i32 1 102 ret i32 %storemerge 103} 104 105define i32 @main3b(i32 %argc) { 106; CHECK-LABEL: @main3b( 107; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 108; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 0 109; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 110; CHECK-NEXT: ret i32 [[STOREMERGE]] 111; 112 %and = and i32 %argc, 7 113 %tobool = icmp eq i32 %and, 0 114 %and2 = and i32 %argc, 16 115 %tobool3 = icmp ne i32 %and2, 16 116 %and.cond = and i1 %tobool, %tobool3 117 %storemerge = select i1 %and.cond, i32 0, i32 1 118 ret i32 %storemerge 119} 120 121define i32 @main3b_logical(i32 %argc) { 122; CHECK-LABEL: @main3b_logical( 123; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 124; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 0 125; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 126; CHECK-NEXT: ret i32 [[STOREMERGE]] 127; 128 %and = and i32 %argc, 7 129 %tobool = icmp eq i32 %and, 0 130 %and2 = and i32 %argc, 16 131 %tobool3 = icmp ne i32 %and2, 16 132 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 133 %storemerge = select i1 %and.cond, i32 0, i32 1 134 ret i32 %storemerge 135} 136 137define i32 @main3e_like(i32 %argc, i32 %argc2, i32 %argc3) { 138; CHECK-LABEL: @main3e_like( 139; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] 140; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 141; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], 0 142; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 143; CHECK-NEXT: ret i32 [[STOREMERGE]] 144; 145 %and = and i32 %argc, %argc2 146 %tobool = icmp eq i32 %and, 0 147 %and2 = and i32 %argc, %argc3 148 %tobool3 = icmp eq i32 %and2, 0 149 %and.cond = and i1 %tobool, %tobool3 150 %storemerge = select i1 %and.cond, i32 0, i32 1 151 ret i32 %storemerge 152} 153 154define i32 @main3e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { 155; CHECK-LABEL: @main3e_like_logical( 156; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 157; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 0 158; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] 159; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], 0 160; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 161; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 162; CHECK-NEXT: ret i32 [[STOREMERGE]] 163; 164 %and = and i32 %argc, %argc2 165 %tobool = icmp eq i32 %and, 0 166 %and2 = and i32 %argc, %argc3 167 %tobool3 = icmp eq i32 %and2, 0 168 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 169 %storemerge = select i1 %and.cond, i32 0, i32 1 170 ret i32 %storemerge 171} 172 173; (icmp ne (A & B), 0) | (icmp ne (A & D), 0) -> (icmp ne (A & (B|D)), 0) 174define i32 @main3c(i32 %argc) { 175; CHECK-LABEL: @main3c( 176; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 177; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 0 178; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 179; CHECK-NEXT: ret i32 [[STOREMERGE]] 180; 181 %and = and i32 %argc, 7 182 %tobool = icmp ne i32 %and, 0 183 %and2 = and i32 %argc, 48 184 %tobool3 = icmp ne i32 %and2, 0 185 %or.cond = or i1 %tobool, %tobool3 186 %storemerge = select i1 %or.cond, i32 0, i32 1 187 ret i32 %storemerge 188} 189 190define i32 @main3c_logical(i32 %argc) { 191; CHECK-LABEL: @main3c_logical( 192; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 193; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 0 194; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 195; CHECK-NEXT: ret i32 [[STOREMERGE]] 196; 197 %and = and i32 %argc, 7 198 %tobool = icmp ne i32 %and, 0 199 %and2 = and i32 %argc, 48 200 %tobool3 = icmp ne i32 %and2, 0 201 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 202 %storemerge = select i1 %or.cond, i32 0, i32 1 203 ret i32 %storemerge 204} 205 206define i32 @main3d(i32 %argc) { 207; CHECK-LABEL: @main3d( 208; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 209; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 0 210; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 211; CHECK-NEXT: ret i32 [[STOREMERGE]] 212; 213 %and = and i32 %argc, 7 214 %tobool = icmp ne i32 %and, 0 215 %and2 = and i32 %argc, 16 216 %tobool3 = icmp eq i32 %and2, 16 217 %or.cond = or i1 %tobool, %tobool3 218 %storemerge = select i1 %or.cond, i32 0, i32 1 219 ret i32 %storemerge 220} 221 222define i32 @main3d_logical(i32 %argc) { 223; CHECK-LABEL: @main3d_logical( 224; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 225; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 0 226; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 227; CHECK-NEXT: ret i32 [[STOREMERGE]] 228; 229 %and = and i32 %argc, 7 230 %tobool = icmp ne i32 %and, 0 231 %and2 = and i32 %argc, 16 232 %tobool3 = icmp eq i32 %and2, 16 233 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 234 %storemerge = select i1 %or.cond, i32 0, i32 1 235 ret i32 %storemerge 236} 237 238define i32 @main3f_like(i32 %argc, i32 %argc2, i32 %argc3) { 239; CHECK-LABEL: @main3f_like( 240; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] 241; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 242; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP2]], 0 243; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 244; CHECK-NEXT: ret i32 [[STOREMERGE]] 245; 246 %and = and i32 %argc, %argc2 247 %tobool = icmp ne i32 %and, 0 248 %and2 = and i32 %argc, %argc3 249 %tobool3 = icmp ne i32 %and2, 0 250 %or.cond = or i1 %tobool, %tobool3 251 %storemerge = select i1 %or.cond, i32 0, i32 1 252 ret i32 %storemerge 253} 254 255define i32 @main3f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { 256; CHECK-LABEL: @main3f_like_logical( 257; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 258; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 0 259; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] 260; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], 0 261; CHECK-NEXT: [[OR_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false 262; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 263; CHECK-NEXT: ret i32 [[STOREMERGE]] 264; 265 %and = and i32 %argc, %argc2 266 %tobool = icmp ne i32 %and, 0 267 %and2 = and i32 %argc, %argc3 268 %tobool3 = icmp ne i32 %and2, 0 269 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 270 %storemerge = select i1 %or.cond, i32 0, i32 1 271 ret i32 %storemerge 272} 273 274; (icmp eq (A & B), B) & (icmp eq (A & D), D) -> (icmp eq (A & (B|D)), (B|D)) 275define i32 @main4(i32 %argc) { 276; CHECK-LABEL: @main4( 277; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 278; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 55 279; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 280; CHECK-NEXT: ret i32 [[STOREMERGE]] 281; 282 %and = and i32 %argc, 7 283 %tobool = icmp eq i32 %and, 7 284 %and2 = and i32 %argc, 48 285 %tobool3 = icmp eq i32 %and2, 48 286 %and.cond = and i1 %tobool, %tobool3 287 %storemerge = select i1 %and.cond, i32 0, i32 1 288 ret i32 %storemerge 289} 290 291define <2 x i32> @main4_splat(<2 x i32> %argc) { 292; CHECK-LABEL: @main4_splat( 293; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[ARGC:%.*]], splat (i32 55) 294; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne <2 x i32> [[TMP1]], splat (i32 55) 295; CHECK-NEXT: [[STOREMERGE:%.*]] = zext <2 x i1> [[AND_COND]] to <2 x i32> 296; CHECK-NEXT: ret <2 x i32> [[STOREMERGE]] 297; 298 %and = and <2 x i32> %argc, <i32 7, i32 7> 299 %tobool = icmp eq <2 x i32> %and, <i32 7, i32 7> 300 %and2 = and <2 x i32> %argc, <i32 48, i32 48> 301 %tobool3 = icmp eq <2 x i32> %and2, <i32 48, i32 48> 302 %and.cond = and <2 x i1> %tobool, %tobool3 303 %storemerge = select <2 x i1> %and.cond, <2 x i32> <i32 0, i32 0>, <2 x i32> <i32 1, i32 1> 304 ret <2 x i32> %storemerge 305} 306 307define i32 @main4_logical(i32 %argc) { 308; CHECK-LABEL: @main4_logical( 309; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 310; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 55 311; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 312; CHECK-NEXT: ret i32 [[STOREMERGE]] 313; 314 %and = and i32 %argc, 7 315 %tobool = icmp eq i32 %and, 7 316 %and2 = and i32 %argc, 48 317 %tobool3 = icmp eq i32 %and2, 48 318 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 319 %storemerge = select i1 %and.cond, i32 0, i32 1 320 ret i32 %storemerge 321} 322 323define i32 @main4b(i32 %argc) { 324; CHECK-LABEL: @main4b( 325; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 326; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 23 327; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 328; CHECK-NEXT: ret i32 [[STOREMERGE]] 329; 330 %and = and i32 %argc, 7 331 %tobool = icmp eq i32 %and, 7 332 %and2 = and i32 %argc, 16 333 %tobool3 = icmp ne i32 %and2, 0 334 %and.cond = and i1 %tobool, %tobool3 335 %storemerge = select i1 %and.cond, i32 0, i32 1 336 ret i32 %storemerge 337} 338 339define i32 @main4b_logical(i32 %argc) { 340; CHECK-LABEL: @main4b_logical( 341; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 342; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 23 343; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 344; CHECK-NEXT: ret i32 [[STOREMERGE]] 345; 346 %and = and i32 %argc, 7 347 %tobool = icmp eq i32 %and, 7 348 %and2 = and i32 %argc, 16 349 %tobool3 = icmp ne i32 %and2, 0 350 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 351 %storemerge = select i1 %and.cond, i32 0, i32 1 352 ret i32 %storemerge 353} 354 355define i32 @main4e_like(i32 %argc, i32 %argc2, i32 %argc3) { 356; CHECK-LABEL: @main4e_like( 357; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] 358; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 359; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] 360; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 361; CHECK-NEXT: ret i32 [[STOREMERGE]] 362; 363 %and = and i32 %argc, %argc2 364 %tobool = icmp eq i32 %and, %argc2 365 %and2 = and i32 %argc, %argc3 366 %tobool3 = icmp eq i32 %and2, %argc3 367 %and.cond = and i1 %tobool, %tobool3 368 %storemerge = select i1 %and.cond, i32 0, i32 1 369 ret i32 %storemerge 370} 371 372define i32 @main4e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { 373; CHECK-LABEL: @main4e_like_logical( 374; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 375; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], [[ARGC2]] 376; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] 377; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]] 378; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 379; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 380; CHECK-NEXT: ret i32 [[STOREMERGE]] 381; 382 %and = and i32 %argc, %argc2 383 %tobool = icmp eq i32 %and, %argc2 384 %and2 = and i32 %argc, %argc3 385 %tobool3 = icmp eq i32 %and2, %argc3 386 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 387 %storemerge = select i1 %and.cond, i32 0, i32 1 388 ret i32 %storemerge 389} 390 391; (icmp ne (A & B), B) | (icmp ne (A & D), D) -> (icmp ne (A & (B|D)), (B|D)) 392define i32 @main4c(i32 %argc) { 393; CHECK-LABEL: @main4c( 394; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 395; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 55 396; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 397; CHECK-NEXT: ret i32 [[STOREMERGE]] 398; 399 %and = and i32 %argc, 7 400 %tobool = icmp ne i32 %and, 7 401 %and2 = and i32 %argc, 48 402 %tobool3 = icmp ne i32 %and2, 48 403 %or.cond = or i1 %tobool, %tobool3 404 %storemerge = select i1 %or.cond, i32 0, i32 1 405 ret i32 %storemerge 406} 407 408define i32 @main4c_logical(i32 %argc) { 409; CHECK-LABEL: @main4c_logical( 410; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 411; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 55 412; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 413; CHECK-NEXT: ret i32 [[STOREMERGE]] 414; 415 %and = and i32 %argc, 7 416 %tobool = icmp ne i32 %and, 7 417 %and2 = and i32 %argc, 48 418 %tobool3 = icmp ne i32 %and2, 48 419 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 420 %storemerge = select i1 %or.cond, i32 0, i32 1 421 ret i32 %storemerge 422} 423 424define i32 @main4d(i32 %argc) { 425; CHECK-LABEL: @main4d( 426; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 427; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 23 428; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 429; CHECK-NEXT: ret i32 [[STOREMERGE]] 430; 431 %and = and i32 %argc, 7 432 %tobool = icmp ne i32 %and, 7 433 %and2 = and i32 %argc, 16 434 %tobool3 = icmp eq i32 %and2, 0 435 %or.cond = or i1 %tobool, %tobool3 436 %storemerge = select i1 %or.cond, i32 0, i32 1 437 ret i32 %storemerge 438} 439 440define i32 @main4d_logical(i32 %argc) { 441; CHECK-LABEL: @main4d_logical( 442; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 443; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 23 444; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 445; CHECK-NEXT: ret i32 [[STOREMERGE]] 446; 447 %and = and i32 %argc, 7 448 %tobool = icmp ne i32 %and, 7 449 %and2 = and i32 %argc, 16 450 %tobool3 = icmp eq i32 %and2, 0 451 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 452 %storemerge = select i1 %or.cond, i32 0, i32 1 453 ret i32 %storemerge 454} 455 456define i32 @main4f_like(i32 %argc, i32 %argc2, i32 %argc3) { 457; CHECK-LABEL: @main4f_like( 458; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] 459; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 460; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] 461; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 462; CHECK-NEXT: ret i32 [[STOREMERGE]] 463; 464 %and = and i32 %argc, %argc2 465 %tobool = icmp ne i32 %and, %argc2 466 %and2 = and i32 %argc, %argc3 467 %tobool3 = icmp ne i32 %and2, %argc3 468 %or.cond = or i1 %tobool, %tobool3 469 %storemerge = select i1 %or.cond, i32 0, i32 1 470 ret i32 %storemerge 471} 472 473define i32 @main4f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { 474; CHECK-LABEL: @main4f_like_logical( 475; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 476; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], [[ARGC2]] 477; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] 478; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], [[ARGC3]] 479; CHECK-NEXT: [[OR_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false 480; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 481; CHECK-NEXT: ret i32 [[STOREMERGE]] 482; 483 %and = and i32 %argc, %argc2 484 %tobool = icmp ne i32 %and, %argc2 485 %and2 = and i32 %argc, %argc3 486 %tobool3 = icmp ne i32 %and2, %argc3 487 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 488 %storemerge = select i1 %or.cond, i32 0, i32 1 489 ret i32 %storemerge 490} 491 492; (icmp eq (A & B), A) & (icmp eq (A & D), A) -> (icmp eq (A & (B&D)), A) 493define i32 @main5_like(i32 %argc, i32 %argc2) { 494; CHECK-LABEL: @main5_like( 495; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 496; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 7 497; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], 7 498; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 499; CHECK-NEXT: ret i32 [[STOREMERGE]] 500; 501 %and = and i32 %argc, 7 502 %tobool = icmp eq i32 %and, 7 503 %and2 = and i32 %argc2, 7 504 %tobool3 = icmp eq i32 %and2, 7 505 %and.cond = and i1 %tobool, %tobool3 506 %storemerge = select i1 %and.cond, i32 0, i32 1 507 ret i32 %storemerge 508} 509 510define i32 @main5_like_logical(i32 %argc, i32 %argc2) { 511; CHECK-LABEL: @main5_like_logical( 512; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], 7 513; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 7 514; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC2:%.*]], 7 515; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], 7 516; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 517; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 518; CHECK-NEXT: ret i32 [[STOREMERGE]] 519; 520 %and = and i32 %argc, 7 521 %tobool = icmp eq i32 %and, 7 522 %and2 = and i32 %argc2, 7 523 %tobool3 = icmp eq i32 %and2, 7 524 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 525 %storemerge = select i1 %and.cond, i32 0, i32 1 526 ret i32 %storemerge 527} 528 529define i32 @main5e_like(i32 %argc, i32 %argc2, i32 %argc3) { 530; CHECK-LABEL: @main5e_like( 531; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC3:%.*]] 532; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 533; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[ARGC]] 534; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 535; CHECK-NEXT: ret i32 [[STOREMERGE]] 536; 537 %and = and i32 %argc, %argc2 538 %tobool = icmp eq i32 %and, %argc 539 %and2 = and i32 %argc, %argc3 540 %tobool3 = icmp eq i32 %and2, %argc 541 %and.cond = and i1 %tobool, %tobool3 542 %storemerge = select i1 %and.cond, i32 0, i32 1 543 ret i32 %storemerge 544} 545 546define i32 @main5e_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { 547; CHECK-LABEL: @main5e_like_logical( 548; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 549; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], [[ARGC]] 550; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] 551; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC]] 552; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 553; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 554; CHECK-NEXT: ret i32 [[STOREMERGE]] 555; 556 %and = and i32 %argc, %argc2 557 %tobool = icmp eq i32 %and, %argc 558 %and2 = and i32 %argc, %argc3 559 %tobool3 = icmp eq i32 %and2, %argc 560 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 561 %storemerge = select i1 %and.cond, i32 0, i32 1 562 ret i32 %storemerge 563} 564 565; (icmp ne (A & B), A) | (icmp ne (A & D), A) -> (icmp ne (A & (B&D)), A) 566define i32 @main5c_like(i32 %argc, i32 %argc2) { 567; CHECK-LABEL: @main5c_like( 568; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 569; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 7 570; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP2]], 7 571; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 572; CHECK-NEXT: ret i32 [[STOREMERGE]] 573; 574 %and = and i32 %argc, 7 575 %tobool = icmp ne i32 %and, 7 576 %and2 = and i32 %argc2, 7 577 %tobool3 = icmp ne i32 %and2, 7 578 %or.cond = or i1 %tobool, %tobool3 579 %storemerge = select i1 %or.cond, i32 0, i32 1 580 ret i32 %storemerge 581} 582 583define i32 @main5c_like_logical(i32 %argc, i32 %argc2) { 584; CHECK-LABEL: @main5c_like_logical( 585; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], 7 586; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 7 587; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC2:%.*]], 7 588; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], 7 589; CHECK-NEXT: [[OR_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false 590; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 591; CHECK-NEXT: ret i32 [[STOREMERGE]] 592; 593 %and = and i32 %argc, 7 594 %tobool = icmp ne i32 %and, 7 595 %and2 = and i32 %argc2, 7 596 %tobool3 = icmp ne i32 %and2, 7 597 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 598 %storemerge = select i1 %or.cond, i32 0, i32 1 599 ret i32 %storemerge 600} 601 602define i32 @main5f_like(i32 %argc, i32 %argc2, i32 %argc3) { 603; CHECK-LABEL: @main5f_like( 604; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC3:%.*]] 605; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 606; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP2]], [[ARGC]] 607; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 608; CHECK-NEXT: ret i32 [[STOREMERGE]] 609; 610 %and = and i32 %argc, %argc2 611 %tobool = icmp ne i32 %and, %argc 612 %and2 = and i32 %argc, %argc3 613 %tobool3 = icmp ne i32 %and2, %argc 614 %or.cond = or i1 %tobool, %tobool3 615 %storemerge = select i1 %or.cond, i32 0, i32 1 616 ret i32 %storemerge 617} 618 619define i32 @main5f_like_logical(i32 %argc, i32 %argc2, i32 %argc3) { 620; CHECK-LABEL: @main5f_like_logical( 621; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 622; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[AND]], [[ARGC]] 623; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] 624; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], [[ARGC]] 625; CHECK-NEXT: [[OR_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 [[TOBOOL3]], i1 false 626; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 627; CHECK-NEXT: ret i32 [[STOREMERGE]] 628; 629 %and = and i32 %argc, %argc2 630 %tobool = icmp ne i32 %and, %argc 631 %and2 = and i32 %argc, %argc3 632 %tobool3 = icmp ne i32 %and2, %argc 633 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 634 %storemerge = select i1 %or.cond, i32 0, i32 1 635 ret i32 %storemerge 636} 637 638; (icmp eq (A & B), C) & (icmp eq (A & D), E) -> (icmp eq (A & (B|D)), (C|E)) 639; if B, C, D, E are constant, and it's possible 640define i32 @main6(i32 %argc) { 641; CHECK-LABEL: @main6( 642; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 643; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 19 644; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 645; CHECK-NEXT: ret i32 [[STOREMERGE]] 646; 647 %and = and i32 %argc, 7 648 %tobool = icmp eq i32 %and, 3 649 %and2 = and i32 %argc, 48 650 %tobool3 = icmp eq i32 %and2, 16 651 %and.cond = and i1 %tobool, %tobool3 652 %storemerge = select i1 %and.cond, i32 0, i32 1 653 ret i32 %storemerge 654} 655 656define i32 @main6_logical(i32 %argc) { 657; CHECK-LABEL: @main6_logical( 658; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 659; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 19 660; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 661; CHECK-NEXT: ret i32 [[STOREMERGE]] 662; 663 %and = and i32 %argc, 7 664 %tobool = icmp eq i32 %and, 3 665 %and2 = and i32 %argc, 48 666 %tobool3 = icmp eq i32 %and2, 16 667 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 668 %storemerge = select i1 %and.cond, i32 0, i32 1 669 ret i32 %storemerge 670} 671 672define i32 @main6b(i32 %argc) { 673; CHECK-LABEL: @main6b( 674; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 675; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 19 676; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 677; CHECK-NEXT: ret i32 [[STOREMERGE]] 678; 679 %and = and i32 %argc, 7 680 %tobool = icmp eq i32 %and, 3 681 %and2 = and i32 %argc, 16 682 %tobool3 = icmp ne i32 %and2, 0 683 %and.cond = and i1 %tobool, %tobool3 684 %storemerge = select i1 %and.cond, i32 0, i32 1 685 ret i32 %storemerge 686} 687 688define i32 @main6b_logical(i32 %argc) { 689; CHECK-LABEL: @main6b_logical( 690; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 691; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP1]], 19 692; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 693; CHECK-NEXT: ret i32 [[STOREMERGE]] 694; 695 %and = and i32 %argc, 7 696 %tobool = icmp eq i32 %and, 3 697 %and2 = and i32 %argc, 16 698 %tobool3 = icmp ne i32 %and2, 0 699 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 700 %storemerge = select i1 %and.cond, i32 0, i32 1 701 ret i32 %storemerge 702} 703 704; (icmp ne (A & B), C) | (icmp ne (A & D), E) -> (icmp ne (A & (B|D)), (C|E)) 705; if B, C, D, E are constant, and it's possible 706define i32 @main6c(i32 %argc) { 707; CHECK-LABEL: @main6c( 708; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 709; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 19 710; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 711; CHECK-NEXT: ret i32 [[STOREMERGE]] 712; 713 %and = and i32 %argc, 7 714 %tobool = icmp ne i32 %and, 3 715 %and2 = and i32 %argc, 48 716 %tobool3 = icmp ne i32 %and2, 16 717 %or.cond = or i1 %tobool, %tobool3 718 %storemerge = select i1 %or.cond, i32 0, i32 1 719 ret i32 %storemerge 720} 721 722define i32 @main6c_logical(i32 %argc) { 723; CHECK-LABEL: @main6c_logical( 724; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55 725; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 19 726; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 727; CHECK-NEXT: ret i32 [[STOREMERGE]] 728; 729 %and = and i32 %argc, 7 730 %tobool = icmp ne i32 %and, 3 731 %and2 = and i32 %argc, 48 732 %tobool3 = icmp ne i32 %and2, 16 733 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 734 %storemerge = select i1 %or.cond, i32 0, i32 1 735 ret i32 %storemerge 736} 737 738define i32 @main6d(i32 %argc) { 739; CHECK-LABEL: @main6d( 740; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 741; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 19 742; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 743; CHECK-NEXT: ret i32 [[STOREMERGE]] 744; 745 %and = and i32 %argc, 7 746 %tobool = icmp ne i32 %and, 3 747 %and2 = and i32 %argc, 16 748 %tobool3 = icmp eq i32 %and2, 0 749 %or.cond = or i1 %tobool, %tobool3 750 %storemerge = select i1 %or.cond, i32 0, i32 1 751 ret i32 %storemerge 752} 753 754define i32 @main6d_logical(i32 %argc) { 755; CHECK-LABEL: @main6d_logical( 756; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23 757; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 19 758; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[OR_COND_NOT]] to i32 759; CHECK-NEXT: ret i32 [[STOREMERGE]] 760; 761 %and = and i32 %argc, 7 762 %tobool = icmp ne i32 %and, 3 763 %and2 = and i32 %argc, 16 764 %tobool3 = icmp eq i32 %and2, 0 765 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 766 %storemerge = select i1 %or.cond, i32 0, i32 1 767 ret i32 %storemerge 768} 769 770; test parameter permutations 771; (B & A) == B & (D & A) == D 772define i32 @main7a(i32 %argc, i32 %argc2, i32 %argc3) { 773; CHECK-LABEL: @main7a( 774; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]] 775; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 776; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] 777; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 778; CHECK-NEXT: ret i32 [[STOREMERGE]] 779; 780 %and1 = and i32 %argc2, %argc 781 %tobool = icmp eq i32 %and1, %argc2 782 %and2 = and i32 %argc3, %argc 783 %tobool3 = icmp eq i32 %and2, %argc3 784 %and.cond = and i1 %tobool, %tobool3 785 %storemerge = select i1 %and.cond, i32 0, i32 1 786 ret i32 %storemerge 787} 788 789define i32 @main7a_logical(i32 %argc, i32 %argc2, i32 %argc3) { 790; CHECK-LABEL: @main7a_logical( 791; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]] 792; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]] 793; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC]] 794; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC3]] 795; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 796; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 797; CHECK-NEXT: ret i32 [[STOREMERGE]] 798; 799 %and1 = and i32 %argc2, %argc 800 %tobool = icmp eq i32 %and1, %argc2 801 %and2 = and i32 %argc3, %argc 802 %tobool3 = icmp eq i32 %and2, %argc3 803 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 804 %storemerge = select i1 %and.cond, i32 0, i32 1 805 ret i32 %storemerge 806} 807 808; B == (A & B) & D == (A & D) 809define i32 @main7b(i32 %argc, i32 %argc2, i32 %argc3x) { 810; CHECK-LABEL: @main7b( 811; CHECK-NEXT: [[ARGC3:%.*]] = mul i32 [[ARGC3X:%.*]], 42 812; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3]] 813; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 814; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] 815; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 816; CHECK-NEXT: ret i32 [[STOREMERGE]] 817; 818 %argc3 = mul i32 %argc3x, 42 ; thwart complexity-based canonicalization 819 %and1 = and i32 %argc, %argc2 820 %tobool = icmp eq i32 %argc2, %and1 821 %and2 = and i32 %argc, %argc3 822 %tobool3 = icmp eq i32 %argc3, %and2 823 %and.cond = and i1 %tobool, %tobool3 824 %storemerge = select i1 %and.cond, i32 0, i32 1 825 ret i32 %storemerge 826} 827 828define i32 @main7b_logical(i32 %argc, i32 %argc2, i32 %argc3) { 829; CHECK-LABEL: @main7b_logical( 830; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]] 831; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[ARGC2]], [[AND1]] 832; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]] 833; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[ARGC3]], [[AND2]] 834; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 835; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 836; CHECK-NEXT: ret i32 [[STOREMERGE]] 837; 838 %and1 = and i32 %argc, %argc2 839 %tobool = icmp eq i32 %argc2, %and1 840 %and2 = and i32 %argc, %argc3 841 %tobool3 = icmp eq i32 %argc3, %and2 842 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 843 %storemerge = select i1 %and.cond, i32 0, i32 1 844 ret i32 %storemerge 845} 846 847; B == (B & A) & D == (D & A) 848define i32 @main7c(i32 %argc, i32 %argc2, i32 %argc3x) { 849; CHECK-LABEL: @main7c( 850; CHECK-NEXT: [[ARGC3:%.*]] = mul i32 [[ARGC3X:%.*]], 42 851; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3]] 852; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 853; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] 854; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 855; CHECK-NEXT: ret i32 [[STOREMERGE]] 856; 857 %argc3 = mul i32 %argc3x, 42 ; thwart complexity-based canonicalization 858 %and1 = and i32 %argc2, %argc 859 %tobool = icmp eq i32 %argc2, %and1 860 %and2 = and i32 %argc3, %argc 861 %tobool3 = icmp eq i32 %argc3, %and2 862 %and.cond = and i1 %tobool, %tobool3 863 %storemerge = select i1 %and.cond, i32 0, i32 1 864 ret i32 %storemerge 865} 866 867define i32 @main7c_logical(i32 %argc, i32 %argc2, i32 %argc3) { 868; CHECK-LABEL: @main7c_logical( 869; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]] 870; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[ARGC2]], [[AND1]] 871; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC]] 872; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[ARGC3]], [[AND2]] 873; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 874; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 875; CHECK-NEXT: ret i32 [[STOREMERGE]] 876; 877 %and1 = and i32 %argc2, %argc 878 %tobool = icmp eq i32 %argc2, %and1 879 %and2 = and i32 %argc3, %argc 880 %tobool3 = icmp eq i32 %argc3, %and2 881 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 882 %storemerge = select i1 %and.cond, i32 0, i32 1 883 ret i32 %storemerge 884} 885 886; (A & (B & C)) == (B & C) & (A & (D & E)) == (D & E) 887define i32 @main7d(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) { 888; CHECK-LABEL: @main7d( 889; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] 890; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] 891; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[BC]], [[DE]] 892; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 893; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] 894; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 895; CHECK-NEXT: ret i32 [[STOREMERGE]] 896; 897 %bc = and i32 %argc2, %argc4 898 %de = and i32 %argc3, %argc5 899 %and1 = and i32 %argc, %bc 900 %tobool = icmp eq i32 %and1, %bc 901 %and2 = and i32 %argc, %de 902 %tobool3 = icmp eq i32 %and2, %de 903 %and.cond = and i1 %tobool, %tobool3 904 %storemerge = select i1 %and.cond, i32 0, i32 1 905 ret i32 %storemerge 906} 907 908define i32 @main7d_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) { 909; CHECK-LABEL: @main7d_logical( 910; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] 911; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] 912; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC:%.*]], [[BC]] 913; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[BC]] 914; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[DE]] 915; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[DE]] 916; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 917; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 918; CHECK-NEXT: ret i32 [[STOREMERGE]] 919; 920 %bc = and i32 %argc2, %argc4 921 %de = and i32 %argc3, %argc5 922 %and1 = and i32 %argc, %bc 923 %tobool = icmp eq i32 %and1, %bc 924 %and2 = and i32 %argc, %de 925 %tobool3 = icmp eq i32 %and2, %de 926 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 927 %storemerge = select i1 %and.cond, i32 0, i32 1 928 ret i32 %storemerge 929} 930 931; ((B & C) & A) == (B & C) & ((D & E) & A) == (D & E) 932define i32 @main7e(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) { 933; CHECK-LABEL: @main7e( 934; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] 935; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] 936; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[BC]], [[DE]] 937; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 938; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] 939; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 940; CHECK-NEXT: ret i32 [[STOREMERGE]] 941; 942 %bc = and i32 %argc2, %argc4 943 %de = and i32 %argc3, %argc5 944 %and1 = and i32 %bc, %argc 945 %tobool = icmp eq i32 %and1, %bc 946 %and2 = and i32 %de, %argc 947 %tobool3 = icmp eq i32 %and2, %de 948 %and.cond = and i1 %tobool, %tobool3 949 %storemerge = select i1 %and.cond, i32 0, i32 1 950 ret i32 %storemerge 951} 952 953define i32 @main7e_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) { 954; CHECK-LABEL: @main7e_logical( 955; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] 956; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] 957; CHECK-NEXT: [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]] 958; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[BC]] 959; CHECK-NEXT: [[AND2:%.*]] = and i32 [[DE]], [[ARGC]] 960; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[DE]] 961; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 962; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 963; CHECK-NEXT: ret i32 [[STOREMERGE]] 964; 965 %bc = and i32 %argc2, %argc4 966 %de = and i32 %argc3, %argc5 967 %and1 = and i32 %bc, %argc 968 %tobool = icmp eq i32 %and1, %bc 969 %and2 = and i32 %de, %argc 970 %tobool3 = icmp eq i32 %and2, %de 971 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 972 %storemerge = select i1 %and.cond, i32 0, i32 1 973 ret i32 %storemerge 974} 975 976; (B & C) == (A & (B & C)) & (D & E) == (A & (D & E)) 977define i32 @main7f(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) { 978; CHECK-LABEL: @main7f( 979; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] 980; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] 981; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[BC]], [[DE]] 982; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 983; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] 984; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 985; CHECK-NEXT: ret i32 [[STOREMERGE]] 986; 987 %bc = and i32 %argc2, %argc4 988 %de = and i32 %argc3, %argc5 989 %and1 = and i32 %argc, %bc 990 %tobool = icmp eq i32 %bc, %and1 991 %and2 = and i32 %argc, %de 992 %tobool3 = icmp eq i32 %de, %and2 993 %and.cond = and i1 %tobool, %tobool3 994 %storemerge = select i1 %and.cond, i32 0, i32 1 995 ret i32 %storemerge 996} 997 998define i32 @main7f_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) { 999; CHECK-LABEL: @main7f_logical( 1000; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] 1001; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] 1002; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC:%.*]], [[BC]] 1003; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[BC]], [[AND1]] 1004; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC]], [[DE]] 1005; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[DE]], [[AND2]] 1006; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 1007; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 1008; CHECK-NEXT: ret i32 [[STOREMERGE]] 1009; 1010 %bc = and i32 %argc2, %argc4 1011 %de = and i32 %argc3, %argc5 1012 %and1 = and i32 %argc, %bc 1013 %tobool = icmp eq i32 %bc, %and1 1014 %and2 = and i32 %argc, %de 1015 %tobool3 = icmp eq i32 %de, %and2 1016 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 1017 %storemerge = select i1 %and.cond, i32 0, i32 1 1018 ret i32 %storemerge 1019} 1020 1021; (B & C) == ((B & C) & A) & (D & E) == ((D & E) & A) 1022define i32 @main7g(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) { 1023; CHECK-LABEL: @main7g( 1024; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] 1025; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] 1026; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[BC]], [[DE]] 1027; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[ARGC:%.*]], [[TMP1]] 1028; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] 1029; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32 1030; CHECK-NEXT: ret i32 [[STOREMERGE]] 1031; 1032 %bc = and i32 %argc2, %argc4 1033 %de = and i32 %argc3, %argc5 1034 %and1 = and i32 %bc, %argc 1035 %tobool = icmp eq i32 %bc, %and1 1036 %and2 = and i32 %de, %argc 1037 %tobool3 = icmp eq i32 %de, %and2 1038 %and.cond = and i1 %tobool, %tobool3 1039 %storemerge = select i1 %and.cond, i32 0, i32 1 1040 ret i32 %storemerge 1041} 1042 1043define i32 @main7g_logical(i32 %argc, i32 %argc2, i32 %argc3, i32 %argc4, i32 %argc5) { 1044; CHECK-LABEL: @main7g_logical( 1045; CHECK-NEXT: [[BC:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC4:%.*]] 1046; CHECK-NEXT: [[DE:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC5:%.*]] 1047; CHECK-NEXT: [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]] 1048; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[BC]], [[AND1]] 1049; CHECK-NEXT: [[AND2:%.*]] = and i32 [[DE]], [[ARGC]] 1050; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[DE]], [[AND2]] 1051; CHECK-NEXT: [[AND_COND_NOT:%.*]] = select i1 [[TOBOOL]], i1 true, i1 [[TOBOOL3]] 1052; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32 1053; CHECK-NEXT: ret i32 [[STOREMERGE]] 1054; 1055 %bc = and i32 %argc2, %argc4 1056 %de = and i32 %argc3, %argc5 1057 %and1 = and i32 %bc, %argc 1058 %tobool = icmp eq i32 %bc, %and1 1059 %and2 = and i32 %de, %argc 1060 %tobool3 = icmp eq i32 %de, %and2 1061 %and.cond = select i1 %tobool, i1 %tobool3, i1 false 1062 %storemerge = select i1 %and.cond, i32 0, i32 1 1063 ret i32 %storemerge 1064} 1065 1066define i32 @main8(i32 %argc) { 1067; CHECK-LABEL: @main8( 1068; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192 1069; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 0 1070; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND_NOT]], i32 1, i32 2 1071; CHECK-NEXT: ret i32 [[RETVAL_0]] 1072; 1073 %and = and i32 %argc, 64 1074 %tobool = icmp ne i32 %and, 0 1075 %trunc2 = trunc i32 %argc to i8 1076 %tobool3 = icmp slt i8 %trunc2, 0 1077 %or.cond = or i1 %tobool, %tobool3 1078 %retval.0 = select i1 %or.cond, i32 2, i32 1 1079 ret i32 %retval.0 1080} 1081 1082define i32 @main8_logical(i32 %argc) { 1083; CHECK-LABEL: @main8_logical( 1084; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192 1085; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 0 1086; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND_NOT]], i32 1, i32 2 1087; CHECK-NEXT: ret i32 [[RETVAL_0]] 1088; 1089 %and = and i32 %argc, 64 1090 %tobool = icmp ne i32 %and, 0 1091 %trunc2 = trunc i32 %argc to i8 1092 %tobool3 = icmp slt i8 %trunc2, 0 1093 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 1094 %retval.0 = select i1 %or.cond, i32 2, i32 1 1095 ret i32 %retval.0 1096} 1097 1098define i32 @main9(i32 %argc) { 1099; CHECK-LABEL: @main9( 1100; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192 1101; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 192 1102; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 1103; CHECK-NEXT: ret i32 [[RETVAL_0]] 1104; 1105 %and = and i32 %argc, 64 1106 %tobool = icmp ne i32 %and, 0 1107 %trunc2 = trunc i32 %argc to i8 1108 %tobool3 = icmp slt i8 %trunc2, 0 1109 %or.cond = and i1 %tobool, %tobool3 1110 %retval.0 = select i1 %or.cond, i32 2, i32 1 1111 ret i32 %retval.0 1112} 1113 1114define i32 @main9_logical(i32 %argc) { 1115; CHECK-LABEL: @main9_logical( 1116; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192 1117; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 192 1118; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 1119; CHECK-NEXT: ret i32 [[RETVAL_0]] 1120; 1121 %and = and i32 %argc, 64 1122 %tobool = icmp ne i32 %and, 0 1123 %trunc2 = trunc i32 %argc to i8 1124 %tobool3 = icmp slt i8 %trunc2, 0 1125 %or.cond = select i1 %tobool, i1 %tobool3, i1 false 1126 %retval.0 = select i1 %or.cond, i32 2, i32 1 1127 ret i32 %retval.0 1128} 1129 1130define i32 @main10(i32 %argc) { 1131; CHECK-LABEL: @main10( 1132; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192 1133; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 0 1134; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 1135; CHECK-NEXT: ret i32 [[RETVAL_0]] 1136; 1137 %and = and i32 %argc, 64 1138 %tobool = icmp eq i32 %and, 0 1139 %trunc2 = trunc i32 %argc to i8 1140 %tobool3 = icmp sge i8 %trunc2, 0 1141 %or.cond = and i1 %tobool, %tobool3 1142 %retval.0 = select i1 %or.cond, i32 2, i32 1 1143 ret i32 %retval.0 1144} 1145 1146define i32 @main10_logical(i32 %argc) { 1147; CHECK-LABEL: @main10_logical( 1148; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192 1149; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 0 1150; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 1151; CHECK-NEXT: ret i32 [[RETVAL_0]] 1152; 1153 %and = and i32 %argc, 64 1154 %tobool = icmp eq i32 %and, 0 1155 %trunc2 = trunc i32 %argc to i8 1156 %tobool3 = icmp sge i8 %trunc2, 0 1157 %or.cond = select i1 %tobool, i1 %tobool3, i1 false 1158 %retval.0 = select i1 %or.cond, i32 2, i32 1 1159 ret i32 %retval.0 1160} 1161 1162define i32 @main11(i32 %argc) { 1163; CHECK-LABEL: @main11( 1164; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192 1165; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 192 1166; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND_NOT]], i32 1, i32 2 1167; CHECK-NEXT: ret i32 [[RETVAL_0]] 1168; 1169 %and = and i32 %argc, 64 1170 %tobool = icmp eq i32 %and, 0 1171 %trunc2 = trunc i32 %argc to i8 1172 %tobool3 = icmp sge i8 %trunc2, 0 1173 %or.cond = or i1 %tobool, %tobool3 1174 %retval.0 = select i1 %or.cond, i32 2, i32 1 1175 ret i32 %retval.0 1176} 1177 1178define i32 @main11_logical(i32 %argc) { 1179; CHECK-LABEL: @main11_logical( 1180; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192 1181; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 192 1182; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND_NOT]], i32 1, i32 2 1183; CHECK-NEXT: ret i32 [[RETVAL_0]] 1184; 1185 %and = and i32 %argc, 64 1186 %tobool = icmp eq i32 %and, 0 1187 %trunc2 = trunc i32 %argc to i8 1188 %tobool3 = icmp sge i8 %trunc2, 0 1189 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 1190 %retval.0 = select i1 %or.cond, i32 2, i32 1 1191 ret i32 %retval.0 1192} 1193 1194define i32 @main12(i32 %argc) { 1195; CHECK-LABEL: @main12( 1196; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896 1197; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 0 1198; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND_NOT]], i32 1, i32 2 1199; CHECK-NEXT: ret i32 [[RETVAL_0]] 1200; 1201 %trunc = trunc i32 %argc to i16 1202 %tobool = icmp slt i16 %trunc, 0 1203 %trunc2 = trunc i32 %argc to i8 1204 %tobool3 = icmp slt i8 %trunc2, 0 1205 %or.cond = or i1 %tobool, %tobool3 1206 %retval.0 = select i1 %or.cond, i32 2, i32 1 1207 ret i32 %retval.0 1208} 1209 1210define i32 @main12_logical(i32 %argc) { 1211; CHECK-LABEL: @main12_logical( 1212; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896 1213; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 0 1214; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND_NOT]], i32 1, i32 2 1215; CHECK-NEXT: ret i32 [[RETVAL_0]] 1216; 1217 %trunc = trunc i32 %argc to i16 1218 %tobool = icmp slt i16 %trunc, 0 1219 %trunc2 = trunc i32 %argc to i8 1220 %tobool3 = icmp slt i8 %trunc2, 0 1221 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 1222 %retval.0 = select i1 %or.cond, i32 2, i32 1 1223 ret i32 %retval.0 1224} 1225 1226define i32 @main13(i32 %argc) { 1227; CHECK-LABEL: @main13( 1228; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896 1229; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 32896 1230; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 1231; CHECK-NEXT: ret i32 [[RETVAL_0]] 1232; 1233 %trunc = trunc i32 %argc to i16 1234 %tobool = icmp slt i16 %trunc, 0 1235 %trunc2 = trunc i32 %argc to i8 1236 %tobool3 = icmp slt i8 %trunc2, 0 1237 %or.cond = and i1 %tobool, %tobool3 1238 %retval.0 = select i1 %or.cond, i32 2, i32 1 1239 ret i32 %retval.0 1240} 1241 1242define i32 @main13_logical(i32 %argc) { 1243; CHECK-LABEL: @main13_logical( 1244; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896 1245; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 32896 1246; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 1247; CHECK-NEXT: ret i32 [[RETVAL_0]] 1248; 1249 %trunc = trunc i32 %argc to i16 1250 %tobool = icmp slt i16 %trunc, 0 1251 %trunc2 = trunc i32 %argc to i8 1252 %tobool3 = icmp slt i8 %trunc2, 0 1253 %or.cond = select i1 %tobool, i1 %tobool3, i1 false 1254 %retval.0 = select i1 %or.cond, i32 2, i32 1 1255 ret i32 %retval.0 1256} 1257 1258define i32 @main14(i32 %argc) { 1259; CHECK-LABEL: @main14( 1260; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896 1261; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 0 1262; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 1263; CHECK-NEXT: ret i32 [[RETVAL_0]] 1264; 1265 %trunc = trunc i32 %argc to i16 1266 %tobool = icmp sge i16 %trunc, 0 1267 %trunc2 = trunc i32 %argc to i8 1268 %tobool3 = icmp sge i8 %trunc2, 0 1269 %or.cond = and i1 %tobool, %tobool3 1270 %retval.0 = select i1 %or.cond, i32 2, i32 1 1271 ret i32 %retval.0 1272} 1273 1274define i32 @main14_logical(i32 %argc) { 1275; CHECK-LABEL: @main14_logical( 1276; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896 1277; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i32 [[TMP1]], 0 1278; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND]], i32 2, i32 1 1279; CHECK-NEXT: ret i32 [[RETVAL_0]] 1280; 1281 %trunc = trunc i32 %argc to i16 1282 %tobool = icmp sge i16 %trunc, 0 1283 %trunc2 = trunc i32 %argc to i8 1284 %tobool3 = icmp sge i8 %trunc2, 0 1285 %or.cond = select i1 %tobool, i1 %tobool3, i1 false 1286 %retval.0 = select i1 %or.cond, i32 2, i32 1 1287 ret i32 %retval.0 1288} 1289 1290define i32 @main15(i32 %argc) { 1291; CHECK-LABEL: @main15( 1292; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896 1293; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 32896 1294; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND_NOT]], i32 1, i32 2 1295; CHECK-NEXT: ret i32 [[RETVAL_0]] 1296; 1297 %trunc = trunc i32 %argc to i16 1298 %tobool = icmp sge i16 %trunc, 0 1299 %trunc2 = trunc i32 %argc to i8 1300 %tobool3 = icmp sge i8 %trunc2, 0 1301 %or.cond = or i1 %tobool, %tobool3 1302 %retval.0 = select i1 %or.cond, i32 2, i32 1 1303 ret i32 %retval.0 1304} 1305 1306define i32 @main15_logical(i32 %argc) { 1307; CHECK-LABEL: @main15_logical( 1308; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896 1309; CHECK-NEXT: [[OR_COND_NOT:%.*]] = icmp eq i32 [[TMP1]], 32896 1310; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND_NOT]], i32 1, i32 2 1311; CHECK-NEXT: ret i32 [[RETVAL_0]] 1312; 1313 %trunc = trunc i32 %argc to i16 1314 %tobool = icmp sge i16 %trunc, 0 1315 %trunc2 = trunc i32 %argc to i8 1316 %tobool3 = icmp sge i8 %trunc2, 0 1317 %or.cond = select i1 %tobool, i1 true, i1 %tobool3 1318 %retval.0 = select i1 %or.cond, i32 2, i32 1 1319 ret i32 %retval.0 1320} 1321 1322define i1 @no_masks_with_logical_or(i32 %a, i32 %b, i32 noundef %c) { 1323; CHECK-LABEL: @no_masks_with_logical_or( 1324; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[B:%.*]], 63 1325; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[C:%.*]] 1326; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1327; CHECK-NEXT: [[OR2:%.*]] = select i1 [[TMP2]], i1 true, i1 [[CMP2]] 1328; CHECK-NEXT: ret i1 [[OR2]] 1329; 1330 %cmp1 = icmp ne i32 %a, 0 1331 %cmp2 = icmp ne i32 %b, 63 1332 %or1 = select i1 %cmp1, i1 true, i1 %cmp2 1333 %cmp3 = icmp ne i32 %c, 0 1334 %or2 = or i1 %or1, %cmp3 1335 ret i1 %or2 1336} 1337 1338define i1 @no_masks_with_logical_or_commuted(i32 %a, i32 %b, i32 noundef %c) { 1339; CHECK-LABEL: @no_masks_with_logical_or_commuted( 1340; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[B:%.*]], 63 1341; CHECK-NEXT: [[C:%.*]] = or i32 [[C1:%.*]], [[A:%.*]] 1342; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i32 [[C]], 0 1343; CHECK-NEXT: [[OR2:%.*]] = select i1 [[CMP3]], i1 true, i1 [[CMP2]] 1344; CHECK-NEXT: ret i1 [[OR2]] 1345; 1346 %cmp1 = icmp ne i32 %a, 0 1347 %cmp2 = icmp ne i32 %b, 63 1348 %or1 = select i1 %cmp1, i1 true, i1 %cmp2 1349 %cmp3 = icmp ne i32 %c, 0 1350 %or2 = or i1 %cmp3, %or1 1351 ret i1 %or2 1352} 1353 1354define i1 @no_masks_with_logical_or2(i32 %a, i32 %b, i32 noundef %c) { 1355; CHECK-LABEL: @no_masks_with_logical_or2( 1356; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[B:%.*]], 63 1357; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], [[C:%.*]] 1358; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], -1 1359; CHECK-NEXT: [[OR2:%.*]] = select i1 [[TMP2]], i1 true, i1 [[CMP2]] 1360; CHECK-NEXT: ret i1 [[OR2]] 1361; 1362 %cmp1 = icmp ne i32 %a, -1 1363 %cmp2 = icmp ne i32 %b, 63 1364 %or1 = select i1 %cmp1, i1 true, i1 %cmp2 1365 %cmp3 = icmp ne i32 %c, -1 1366 %or2 = or i1 %or1, %cmp3 1367 ret i1 %or2 1368} 1369 1370define <2 x i1> @no_masks_with_logical_or_vec_poison1(<2 x i32> %a, <2 x i32> %b, <2 x i32> noundef %c) { 1371; CHECK-LABEL: @no_masks_with_logical_or_vec_poison1( 1372; CHECK-NEXT: [[CMP2:%.*]] = icmp ne <2 x i32> [[B:%.*]], <i32 63, i32 poison> 1373; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[A:%.*]], [[C:%.*]] 1374; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer 1375; CHECK-NEXT: [[OR2:%.*]] = select <2 x i1> [[TMP2]], <2 x i1> splat (i1 true), <2 x i1> [[CMP2]] 1376; CHECK-NEXT: ret <2 x i1> [[OR2]] 1377; 1378 %cmp1 = icmp ne <2 x i32> %a, <i32 0, i32 poison> 1379 %cmp2 = icmp ne <2 x i32> %b, <i32 63, i32 poison> 1380 %or1 = select <2 x i1> %cmp1, <2 x i1> <i1 true, i1 true>, <2 x i1> %cmp2 1381 %cmp3 = icmp ne <2 x i32> %c, <i32 0, i32 poison> 1382 %or2 = or <2 x i1> %or1, %cmp3 1383 ret <2 x i1> %or2 1384} 1385 1386define <2 x i1> @no_masks_with_logical_or_vec_poison2(<2 x i32> %a, <2 x i32> %b, <2 x i32> noundef %c) { 1387; CHECK-LABEL: @no_masks_with_logical_or_vec_poison2( 1388; CHECK-NEXT: [[CMP2:%.*]] = icmp ne <2 x i32> [[B:%.*]], <i32 63, i32 poison> 1389; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], [[C:%.*]] 1390; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], splat (i32 -1) 1391; CHECK-NEXT: [[OR2:%.*]] = select <2 x i1> [[TMP2]], <2 x i1> splat (i1 true), <2 x i1> [[CMP2]] 1392; CHECK-NEXT: ret <2 x i1> [[OR2]] 1393; 1394 %cmp1 = icmp ne <2 x i32> %a, <i32 -1, i32 poison> 1395 %cmp2 = icmp ne <2 x i32> %b, <i32 63, i32 poison> 1396 %or1 = select <2 x i1> %cmp1, <2 x i1> <i1 true, i1 true>, <2 x i1> %cmp2 1397 %cmp3 = icmp ne <2 x i32> %c, <i32 -1, i32 poison> 1398 %or2 = or <2 x i1> %or1, %cmp3 1399 ret <2 x i1> %or2 1400} 1401 1402define i1 @only_one_masked(i64 %a) { 1403; CHECK-LABEL: @only_one_masked( 1404; CHECK-NEXT: [[AND:%.*]] = icmp eq i64 [[A:%.*]], -9223372036854775808 1405; CHECK-NEXT: ret i1 [[AND]] 1406; 1407 %cmp1 = icmp ne i64 %a, 0 1408 %a.mask = and i64 %a, 9223372036854775807 1409 %cmp2 = icmp eq i64 %a.mask, 0 1410 %and = and i1 %cmp1, %cmp2 1411 ret i1 %and 1412} 1413