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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
15 field bits<32> Inst;
16 field bits<32> SoftFail = 0;
22 let Inst{0-5} = opcode;
28 bits<1> PPC970_First = 0;
29 bits<1> PPC970_Single = 0;
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrFormats.td1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
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H A DMicroMipsInstrFormats.td1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
40 // Base class for MicroMIPS 16-bit instructions.
47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
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H A DMipsDSPInstrFormats.td1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
23 def HasDSP : Predicate<"Subtarget->hasDSP()">,
25 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
27 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
39 class Field6<bits<6> val> {
40 bits<6> V = val;
64 // ADDU.QB sub-class format.
65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
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H A DMicroMips32r6InstrFormats.td1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
35 //===----------------------------------------------------------------------===//
38 bits<10> offset;
40 bits<16> Inst;
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H A DMicroMipsDSPInstrFormats.td1 //===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
24 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
25 bits<5> rd;
26 bits<5> rs;
27 bits<5> rt;
29 let Inst{31-26} = 0b000000;
30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
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H A DMipsInstrFormats.td1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
14 // opcode - operation code.
15 // rs - src reg.
16 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
17 // rd - dst reg, only used on 3 regs instr.
18 // shamt - only used on shift instructions, contains the shift amount.
19 // funct - combined with opcode field give us an operation code.
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H A DMips16InstrFormats.td1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
16 // immediate 4-,5-,8- or 11-bit immediate, branch displacement, or
19 // op 5-bit major operation code
21 // rx 3-bit source or destination register
23 // ry 3-bit source or destination register
25 // rz 3-bit source or destination register
27 // sa 3- or 5-bit shift amount
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H A DMips32r6InstrFormats.td1 //=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exceptio
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H A DMipsMTInstrFormats.td1 //===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rt - destination register
15 //===----------------------------------------------------------------------===//
22 class OPCODE1<bits<1> Val> {
23 bits<1> Value = Val;
29 class FIELD5<bits<5> Val> {
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrFormats.td1 // LoongArchLSXInstrFormats.td - LoongArch LSX Instr Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // vd/rd/cd - destination register operand.
14 // {r/v}{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
19 // 1RI13-type
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H A DLoongArchLASXInstrFormats.td1 // LoongArchLASXInstrFormats.td - LoongArch LASX Instr Formats - tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // xd/rd/cd - destination register operand.
14 // {r/x}{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
19 // 1RI13-type
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H A DLoongArchInstrFormats.td1 //===- LoongArchInstrFormats.td - LoongArch Instr. Formats -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rd - destination register operand.
14 // r{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
22 field bits<32> Inst;
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H A DLoongArchLBTInstrFormats.td1 // LoongArchLBTInstrFormats.td - LoongArch LBT Instr Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rd/sd - destination register operand.
14 // rj/rk/sj - source register operand.
15 // immN/ptr - immediate data operand.
23 //===----------------------------------------------------------------------===//
25 // 1R-type (no outs)
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H A DLoongArchFloatInstrFormats.td1 // LoongArchFloatInstrFormats.td - LoongArch FP Instr Formats -*- tablegen -*-//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // Describe LoongArch floating-point instructions format
12 // opcode - operation code.
13 // fd - destination register operand.
14 // {c/f}{j/k/a} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td1 //===- CSKYInstrFormats16Instr.td - 16-bit Instr. Formats -*- tablegen --*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 class J16<bits<5> sop, string opstr, dag ins>
12 bits<10> offset;
14 let Inst{14 - 10} = sop;
15 let Inst{9 - 0} = offset;
18 class J16_B<bits<5> sop, string opstr>
21 bits<10> offset;
23 let Inst{14 - 10} = sop;
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H A DCSKYInstrFormats.td1 //===-- CSKYInstrFormats.td - CSKY Instruction Formats -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 class AddrMode<bits<5> val> {
10 bits<5> Value = val;
27 field bits<32> SoftFail = 0;
33 let TSFlags{4 - 0} = AM.Value;
42 class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
45 field bits<32> Inst;
46 let Inst{31 - 26} = opcode;
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H A DCSKYInstrFormatsF2.td1 //===- CSKYInstrFormatsF2.td - CSKY Float2.0 Instr Format --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
23 bits<5> vry;
24 bits<5> vrx;
25 bits<5> vrz;
27 let Inst{25-21} = vry;
28 let Inst{20-16} = vrx;
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td1 //===-- RISCVInstrFormatsC.td - RISC-V C Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V C extension instruction formats.
11 //===----------------------------------------------------------------------===//
16 field bits<16> Inst;
21 field bits<16> SoftFail = 0;
25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
28 bits<5> rs1;
29 bits<5> rs2;
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 bits <5> Vu32;
13 let Inst{12-8} = Vu32{4-0};
14 bits <5> Rt32;
15 let Inst{20-16} = Rt32{4-0};
16 bits <5> Vdd32;
17 let Inst{4-0} = Vdd32{4-0};
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 field bits<64> Inst;
15 field bits<64> SoftFail = 0;
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;
16 "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
26 field bits<64> Inst;
30 bits<2> FlagOperandIdx = 0;
59 let TSFlags{8-7} = FlagOperandIdx;
61 let TSFlags{10} = Op1;
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H A DVOPInstructions.td1 //===-- VOPInstructions.td - Vector Instruction Definitions -------
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td1 //===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 field bits<32> Inst;
22 field bits<32> SoftFail = 0;
31 //===----------------------------------------------------------------------===//
33 //===----------------------------------------------------------------------===//
35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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/freebsd-src/contrib/file/magic/Magdir/
H A Darm1 #----------
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