Lines Matching +full:10 +full:- +full:bits
1 //===- LoongArchInstrFormats.td - LoongArch Instr. Formats -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rd - destination register operand.
14 // r{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
22 field bits<32> Inst;
27 field bits<32> SoftFail = 0;
49 // 2R-type
51 class Fmt2R<bits<32> op, dag outs, dag ins, string opnstr,
54 bits<5> rj;
55 bits<5> rd;
57 let Inst{31-0} = op;
58 let Inst{9-5} = rj;
59 let Inst{4-0} = rd;
62 // 3R-type
64 class Fmt3R<bits<32> op, dag outs, dag ins, string opnstr,
67 bits<5> rk;
68 bits<5> rj;
69 bits<5> rd;
71 let Inst{31-0} = op;
72 let Inst{14-10} = rk;
73 let Inst{9-5} = rj;
74 let Inst{4-0} = rd;
77 // 3RI2-type
79 class Fmt3RI2<bits<32> op, dag outs, dag ins, string opnstr,
82 bits<2> imm2;
83 bits<5> rk;
84 bits<5> rj;
85 bits<5> rd;
87 let Inst{31-0} = op;
88 let Inst{16-15} = imm2;
89 let Inst{14-10} = rk;
90 let Inst{9-5} = rj;
91 let Inst{4-0} = rd;
94 // 3RI3-type
96 class Fmt3RI3<bits<32> op, dag outs, dag ins, string opnstr,
99 bits<3> imm3;
100 bits<5> rk;
101 bits<5> rj;
102 bits<5> rd;
104 let Inst{31-0} = op;
105 let Inst{17-15} = imm3;
106 let Inst{14-10} = rk;
107 let Inst{9-5} = rj;
108 let Inst{4-0} = rd;
111 // 2RI5-type
113 class Fmt2RI5<bits<32> op, dag outs, dag ins, string opnstr,
116 bits<5> imm5;
117 bits<5> rj;
118 bits<5> rd;
120 let Inst{31-0} = op;
121 let Inst{14-10} = imm5;
122 let Inst{9-5} = rj;
123 let Inst{4-0} = rd;
126 // 2RI6-type
128 class Fmt2RI6<bits<32> op, dag outs, dag ins, string opnstr,
131 bits<6> imm6;
132 bits<5> rj;
133 bits<5> rd;
135 let Inst{31-0} = op;
136 let Inst{15-10} = imm6;
137 let Inst{9-5} = rj;
138 let Inst{4-0} = rd;
141 // 2RI8-type
143 class Fmt2RI8<bits<32> op, dag outs, dag ins, string opnstr,
146 bits<8> imm8;
147 bits<5> rj;
148 bits<5> rd;
150 let Inst{31-0} = op;
151 let Inst{17-10} = imm8;
152 let Inst{9-5} = rj;
153 let Inst{4-0} = rd;
156 // 2RI12-type
158 class Fmt2RI12<bits<32> op, dag outs, dag ins, string opnstr,
161 bits<12> imm12;
162 bits<5> rj;
163 bits<5> rd;
165 let Inst{31-0} = op;
166 let Inst{21-10} = imm12;
167 let Inst{9-5} = rj;
168 let Inst{4-0} = rd;
171 // 2RI14-type
173 class Fmt2RI14<bits<32> op, dag outs, dag ins, string opnstr,
176 bits<14> imm14;
177 bits<5> rj;
178 bits<5> rd;
180 let Inst{31-0} = op;
181 let Inst{23-10} = imm14;
182 let Inst{9-5} = rj;
183 let Inst{4-0} = rd;
186 // 2RI16-type
188 class Fmt2RI16<bits<32> op, dag outs, dag ins, string opnstr,
191 bits<16> imm16;
192 bits<5> rj;
193 bits<5> rd;
195 let Inst{31-0} = op;
196 let Inst{25-10} = imm16;
197 let Inst{9-5} = rj;
198 let Inst{4-0} = rd;
201 // 1RI20-type
203 class Fmt1RI20<bits<32> op, dag outs, dag ins, string opnstr,
206 bits<20> imm20;
207 bits<5> rd;
209 let Inst{31-0} = op;
210 let Inst{24-5} = imm20;
211 let Inst{4-0} = rd;
214 // 1RI21-type
216 class Fmt1RI21<bits<32> op, dag outs, dag ins, string opnstr,
219 bits<21> imm21;
220 bits<5> rj;
222 let Inst{31-0} = op;
223 let Inst{25-10} = imm21{15-0};
224 let Inst{9-5} = rj;
225 let Inst{4-0} = imm21{20-16};
228 // I15-type
230 class FmtI15<bits<32> op, dag outs, dag ins, string opnstr,
233 bits<15> imm15;
235 let Inst{31-0} = op;
236 let Inst{14-0} = imm15;
239 // I26-type
241 class FmtI26<bits<32> op, dag outs, dag ins, string opnstr,
244 bits<26> imm26;
246 let Inst{31-0} = op;
247 let Inst{25-10} = imm26{15-0};
248 let Inst{9-0} = imm26{25-16};
253 class FmtBSTR_W<bits<32> op, dag outs, dag ins, string opnstr,
256 bits<5> msbw;
257 bits<5> lsbw;
258 bits<5> rj;
259 bits<5> rd;
261 let Inst{31-0} = op;
262 let Inst{20-16} = msbw;
263 let Inst{14-10} = lsbw;
264 let Inst{9-5} = rj;
265 let Inst{4-0} = rd;
270 class FmtBSTR_D<bits<32> op, dag outs, dag ins, string opnstr,
273 bits<6> msbd;
274 bits<6> lsbd;
275 bits<5> rj;
276 bits<5> rd;
278 let Inst{31-0} = op;
279 let Inst{21-16} = msbd;
280 let Inst{15-10} = lsbd;
281 let Inst{9-5} = rj;
282 let Inst{4-0} = rd;
287 class FmtASRT<bits<32> op, dag outs, dag ins, string opnstr,
290 bits<5> rk;
291 bits<5> rj;
293 let Inst{31-0} = op;
294 let Inst{14-10} = rk;
295 let Inst{9-5} = rj;
302 bits<12> imm12;
303 bits<5> rj;
304 bits<5> imm5;
306 let Inst{31-22} = 0b0010101011;
307 let Inst{21-10} = imm12;
308 let Inst{9-5} = rj;
309 let Inst{4-0} = imm5;
316 bits<5> rk;
317 bits<5> rj;
318 bits<5> imm5;
320 let Inst{31-15} = 0b00111000001011000;
321 let Inst{14-10} = rk;
322 let Inst{9-5} = rj;
323 let Inst{4-0} = imm5;
328 class FmtCSR<bits<32> op, dag outs, dag ins, string opnstr,
331 bits<14> csr_num;
332 bits<5> rd;
334 let Inst{31-0} = op;
335 let Inst{23-10} = csr_num;
336 let Inst{4-0} = rd;
341 class FmtCSRXCHG<bits<32> op, dag outs, dag ins, string opnstr,
344 bits<14> csr_num;
345 bits<5> rj;
346 bits<5> rd;
348 let Inst{31-0} = op;
349 let Inst{23-10} = csr_num;
350 let Inst{9-5} = rj;
351 let Inst{4-0} = rd;
358 bits<12> imm12;
359 bits<5> rj;
360 bits<5> op;
362 let Inst{31-22} = 0b0000011000;
363 let Inst{21-10} = imm12;
364 let Inst{9-5} = rj;
365 let Inst{4-0} = op;
370 class FmtI32<bits<32> op, list<dag> pattern = []>
372 let Inst{31-0} = op;
379 bits<5> rk;
380 bits<5> rj;
381 bits<5> op;
383 let Inst{31-15} = 0b00000110010010011;
384 let Inst{14-10} = rk;
385 let Inst{9-5} = rj;
386 let Inst{4-0} = op;
393 bits<8> seq;
394 bits<5> rj;
396 let Inst{31-18} = 0b00000110010001;
397 let Inst{17-10} = seq;
398 let Inst{9-5} = rj;
399 let Inst{4-0} = 0b00000;