Lines Matching +full:10 +full:- +full:bits
1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
16 // immediate 4-,5-,8- or 11-bit immediate, branch displacement, or
19 // op 5-bit major operation code
21 // rx 3-bit source or destination register
23 // ry 3-bit source or destination register
25 // rz 3-bit source or destination register
27 // sa 3- or 5-bit shift amount
29 //===----------------------------------------------------------------------===//
58 field bits<16> Inst;
59 bits<5> Opcode = 0;
61 // Top 5 bits are the 'opcode' field
62 let Inst{15-11} = Opcode;
65 field bits<16> SoftFail = 0;
75 field bits<32> Inst;
78 field bits<32> SoftFail = 0;
85 let Inst{31-27} = 0b11110;
98 //===----------------------------------------------------------------------===//
100 //===----------------------------------------------------------------------===//
102 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
106 bits<11> imm11;
110 let Inst{10-0} = imm11;
113 //===----------------------------------------------------------------------===//
115 //===----------------------------------------------------------------------===//
117 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
121 bits<3> rx;
122 bits<8> imm8;
126 let Inst{10-8} = rx;
127 let Inst{7-0} = imm8;
130 //===----------------------------------------------------------------------===//
132 //===----------------------------------------------------------------------===//
134 class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
138 bits<3> rx;
139 bits<3> ry;
140 bits<5> funct;
145 let Inst{10-8} = rx;
146 let Inst{7-5} = ry;
147 let Inst{4-0} = funct;
154 bits<6> Code;
155 bits<5> funct;
160 let Inst{10-5} = Code;
161 let Inst{4-0} = funct;
167 class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
171 bits<3> rx;
172 bits<3> subfunct;
173 bits<5> funct;
179 let Inst{10-8} = rx;
180 let Inst{7-5} = subfunct;
181 let Inst{4-0} = funct;
187 class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
191 bits<6> _code; // code is a keyword in tablegen
192 bits<5> funct;
197 let Inst{10-5} = _code;
198 let Inst{4-0} = funct;
204 class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
209 bits<3> rx;
210 bits<1> nd;
211 bits<1> l;
212 bits<1> ra;
220 let Inst{10-8} = rx;
224 let Inst{4-0} = 0;
227 //===----------------------------------------------------------------------===//
229 //===----------------------------------------------------------------------===//
231 class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
235 bits<3> rx;
236 bits<3> ry;
237 bits<5> imm5;
242 let Inst{10-8} = rx;
243 let Inst{7-5} = ry;
244 let Inst{4-0} = imm5;
247 //===----------------------------------------------------------------------===//
249 //===----------------------------------------------------------------------===//
251 class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
255 bits<3> rx;
256 bits<3> ry;
257 bits<3> rz;
258 bits<2> f;
263 let Inst{10-8} = rx;
264 let Inst{7-5} = ry;
265 let Inst{4-2} = rz;
266 let Inst{1-0} = f;
269 //===----------------------------------------------------------------------===//
270 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
271 //===----------------------------------------------------------------------===//
273 class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
277 bits<3> rx;
278 bits<3> ry;
279 bits<1> f;
280 bits<4> imm4;
285 let Inst{10-8} = rx;
286 let Inst{7-5} = ry;
288 let Inst{3-0} = imm4;
291 //===----------------------------------------------------------------------===//
293 //===----------------------------------------------------------------------===//
295 class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
299 bits<3> rx;
300 bits<3> ry;
301 bits<3> sa;
302 bits<2> f;
307 let Inst{10-8} = rx;
308 let Inst{7-5} = ry;
309 let Inst{4-2} = sa;
310 let Inst{1-0} = f;
313 //===----------------------------------------------------------------------===//
315 //===----------------------------------------------------------------------===//
317 class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
321 bits<3> func;
322 bits<8> imm8;
327 let Inst{10-8} = func;
328 let Inst{7-0} = imm8;
331 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
339 // FIXME: this seems wrong? 'ry' should be 3 bits, and 'r32' 5?
340 bits<4> ry;
341 bits<4> r32;
345 let Inst{10-8} = 0b111;
346 let Inst{7-4} = ry;
347 let Inst{3-0} = r32;
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
362 bits<3> func;
363 bits<5> r32;
364 bits<3> rz;
369 let Inst{10-8} = 0b101;
370 let Inst{7-5} = r32{2-0};
371 let Inst{4-3} = r32{4-3};
372 let Inst{2-0} = rz;
376 //===----------------------------------------------------------------------===//
379 //===----------------------------------------------------------------------===//
381 class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
385 bits<1> s;
386 bits<1> ra = 0;
387 bits<1> s0 = 0;
388 bits<1> s1 = 0;
389 bits<4> framesize = 0;
394 let Inst{10-8} = 0b100;
399 let Inst{3-0} = framesize;
403 //===----------------------------------------------------------------------===//
406 //===----------------------------------------------------------------------===//
408 class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
412 bits<1> X;
413 bits<26> imm26;
418 let Inst{31-27} = 0b00011;
420 let Inst{25-21} = imm26{20-16};
421 let Inst{20-16} = imm26{25-21};
422 let Inst{15-0} = imm26{15-0};
426 //===----------------------------------------------------------------------===//
427 // Format EXT-I instruction class in Mips16 :
429 //===----------------------------------------------------------------------===//
431 class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
435 bits<16> imm16;
436 bits<5> eop;
440 let Inst{26-21} = imm16{10-5};
441 let Inst{20-16} = imm16{15-11};
442 let Inst{15-11} = eop;
443 let Inst{10-5} = 0;
444 let Inst{4-0} = imm16{4-0};
448 //===----------------------------------------------------------------------===//
451 //===----------------------------------------------------------------------===//
457 bits<3> select;
458 bits<3> p4;
459 bits<5> p3;
460 bits<5> RRR = 0b11100;
461 bits<3> p2;
462 bits<3> p1;
463 bits<5> p0;
466 let Inst{26-24} = select;
467 let Inst{23-21} = p4;
468 let Inst{20-16} = p3;
469 let Inst{15-11} = RRR;
470 let Inst{10-8} = p2;
471 let Inst{7-5} = p1;
472 let Inst{4-0} = p0;
477 //===----------------------------------------------------------------------===//
478 // Format EXT-RI instruction class in Mips16 :
480 //===----------------------------------------------------------------------===//
482 class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
486 bits<16> imm16;
487 bits<5> op;
488 bits<3> rx;
492 let Inst{26-21} = imm16{10-5};
493 let Inst{20-16} = imm16{15-11};
494 let Inst{15-11} = op;
495 let Inst{10-8} = rx;
496 let Inst{7-5} = 0;
497 let Inst{4-0} = imm16{4-0};
501 //===----------------------------------------------------------------------===//
502 // Format EXT-RRI instruction class in Mips16 :
504 //===----------------------------------------------------------------------===//
506 class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
510 bits<5> op;
511 bits<16> imm16;
512 bits<3> rx;
513 bits<3> ry;
517 let Inst{26-21} = imm16{10-5};
518 let Inst{20-16} = imm16{15-11};
519 let Inst{15-11} = op;
520 let Inst{10-8} = rx;
521 let Inst{7-5} = ry;
522 let Inst{4-0} = imm16{4-0};
526 //===----------------------------------------------------------------------===//
527 // Format EXT-RRI-A instruction class in Mips16 :
528 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
529 //===----------------------------------------------------------------------===//
531 class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
535 bits<15> imm15;
536 bits<3> rx;
537 bits<3> ry;
538 bits<1> f;
542 let Inst{26-20} = imm15{10-4};
543 let Inst{19-16} = imm15{14-11};
544 let Inst{15-11} = 0b01000;
545 let Inst{10-8} = rx;
546 let Inst{7-5} = ry;
548 let Inst{3-0} = imm15{3-0};
552 //===----------------------------------------------------------------------===//
553 // Format EXT-SHIFT instruction class in Mips16 :
555 //===----------------------------------------------------------------------===//
557 class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
561 bits<6> sa6;
562 bits<3> rx;
563 bits<3> ry;
564 bits<2> f;
568 let Inst{26-22} = sa6{4-0};
570 let Inst{20-16} = 0;
571 let Inst{15-11} = 0b00110;
572 let Inst{10-8} = rx;
573 let Inst{7-5} = ry;
574 let Inst{4-2} = 0;
575 let Inst{1-0} = f;
579 //===----------------------------------------------------------------------===//
580 // Format EXT-I8 instruction class in Mips16 :
582 //===----------------------------------------------------------------------===//
584 class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
588 bits<16> imm16;
589 bits<5> I8;
590 bits<3> funct;
595 let Inst{26-21} = imm16{10-5};
596 let Inst{20-16} = imm16{15-11};
597 let Inst{15-11} = I8;
598 let Inst{10-8} = funct;
599 let Inst{7-5} = 0;
600 let Inst{4-0} = imm16{4-0};
604 //===----------------------------------------------------------------------===//
605 // Format EXT-I8_SVRS instruction class in Mips16 :
607 //===----------------------------------------------------------------------===//
609 class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
613 bits<3> xsregs =0;
614 bits<8> framesize =0;
615 bits<3> aregs =0;
616 bits<5> I8 = 0b01100;
617 bits<3> SVRS = 0b100;
618 bits<1> s;
619 bits<1> ra = 0;
620 bits<1> s0 = 0;
621 bits<1> s1 = 0;
625 let Inst{26-24} = xsregs;
626 let Inst{23-20} = framesize{7-4};
628 let Inst{18-16} = aregs;
629 let Inst{15-11} = I8;
630 let Inst{10-8} = SVRS;
635 let Inst{3-0} = framesize{3-0};