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/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dspill-wide-sgpr.ll1 ; RUN: llc -O0 -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN …
2 ; RUN: llc -O0 -mtriple=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s |…
4 ; GCN-LABEL: {{^}}spill_sgpr_x2:
6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
18 define amdgpu_kernel void @spill_sgpr_x2(ptr addrspace(1) %out, i32 %in) #0 {
19 %wide.sgpr = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
20 %cmp = icmp eq i32 %in, 0
[all …]
H A Dllvm.amdgcn.mfma.ll1 ; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope --…
2 … llc -mtriple=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug -verify-machineinstrs < %s | Fil…
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope --…
4 ; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -enable-var-scope --…
21 ; GCN-LABEL: {{^}}test_mfma_f32_32x32x1f32:
22 ; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
23 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
24 ; GCN-DAG: s_load_dwordx16
25 ; GCN-DAG: s_load_dwordx16
26 ; GFX908-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
[all …]
H A Dfma.f64.ll1 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCh…
2 …RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global …
3 …UN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx90a -mattr=-flat-for-global …
4 …UN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global…
11 ; FUNC-LABEL: {{^}}fma_f64:
12 ; SIGFX11: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+…
13 ; GFX90A: v_fmac_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
24 ; FUNC-LABEL: {{^}}fma_v2f64:
25 ; SIGFX11: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
26 ; SIGFX11: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
[all …]
H A Dpermlane16_opsel.ll1 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 --stop-after=amdgpu-isel -verif
[all...]
H A Dfsub64.ll1 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstr…
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs…
4 declare double @llvm.fabs.f64(double) #0
6 ; SI-LABEL: {{^}}fsub_f64:
7 ; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
17 ; SI-LABEL: {{^}}fsub_fabs_f64:
18 ; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|}}
23 %r1.fabs = call double @llvm.fabs.f64(double %r1) #0
29 ; SI-LABEL: {{^}}fsub_fabs_inv_f64:
30 ; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, -v\[[0-9]+:[0-9]+\]}}
[all …]
H A Dmad-combine.ll1 ; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma.
3 …-mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | File…
4 …-mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -verify-machineinstrs -fp-contrac…
5 …-mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -verify-machineinstrs -enable-uns…
7 ; FIXME: Remove enable-unsafe-fp-math in RUN line and add flags to IR instrs
10 …-mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee -fp-contract=fast -verify-machineinstrs < …
11 …-mtriple=amdgcn -mcpu=verde -denormal-fp-math-f32=ieee -fp-contract=fast -verify-machineinstrs < %…
13 declare i32 @llvm.amdgcn.workitem.id.x() #0
14 declare float @llvm.fabs.f32(float) #0
15 declare float @llvm.fma.f32(float, float, float) #0
[all …]
H A Dllvm.amdgcn.mfma.gfx90a.ll1 ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope --…
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -enable-var-scope --…
13 ; GCN-LABEL: {{^}}test_mfma_f32_32x32x4bf16_1k:
14 ; GCN-DAG: s_load_dwordx16
15 ; GCN-DAG: s_load_dwordx16
16 ; GCN-DAG: v_mov_b32_e32 v[[TWO:[0-9]+]], 2
17 ; GCN-DAG: v_mov_b32_e32 v[[ONE:[0-9]+]], 1
18 ; GCN-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
19 … v_mfma_f32_32x32x4bf16_1k a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}]…
20 … v_mfma_f32_32x32x4_2b_bf16 a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9+]}}], v[[[TWO]]:{{[0-9+]}}]…
[all …]
H A Dllvm.amdgcn.mfma.gfx940.ll1 ; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixe
[all...]
H A Dv_mac_f16.ll1 …-amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | Fil…
2 …-amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-ma…
4 ; GCN-LABEL: {{^}}mac_f16:
5 ; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
6 ; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
7 ; GCN: {{buffer|flat}}_load_ushort v[[C_F16:[0-9]+]]
8 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10 ; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
12 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]]
[all …]
H A Dsalu-to-valu.ll1 …-amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | Fi…
2 …-amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | F…
3 …-amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=bonaire -verify-machineinstrs …
5 declare i32 @llvm.amdgcn.workitem.id.x() #0
6 declare i32 @llvm.amdgcn.workitem.id.y() #0
11 ; result in the offset operand (vaddr), and then store 0 in an
13 ; (low 64-bits of srsrc).
15 ; GCN-LABEL: {{^}}mubuf:
18 ; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
22 ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dvec_cmpq.ll3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
4 ; RUN: -mcpu=pwr10 < %s | FileCheck %s
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr10 -mattr=-vsx < %s | FileCheck %s
7 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
8 ; RUN: -mcpu=pwr10 < %s | FileCheck %s
13 ; CHECK-LABEL: v1si128_cmp:
21 ; CHECK-LABEL: v2si128_cmp
22 ; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
23 ; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
[all …]
H A Dvec_cmpd.ll3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s |…
10 ; CHECK-LABEL: v2si64_cmp:
18 ; CHECK-LABEL: v4si64_cmp
19 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
20 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
27 ; CHECK-LABEL: v8si64_cmp
28 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
29 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
30 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dfp-dp3.ll1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -fp-contract=fast | FileCh…
2 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s -check-prefix=C…
8 ; CHECK-LABEL: test_fmadd:
9 ; CHECK-NOFAST-LABEL: test_fmadd:
11 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
12 ; CHECK-NOFAST: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
17 ; CHECK-LABEL: test_fmsub:
18 ; CHECK-NOFAST-LABEL: test_fmsub:
19 %nega = fsub float -0.0, %a
21 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
[all …]
/llvm-project/clang/test/CodeGenOpenCL/
H A Damdgpu-debug-info-variable-expression.cl1 // REQUIRES: amdgpu-registered-target
2 // RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -nogpulib -target amdgcn-amd-amdhsa -mcpu=fiji -o…
3 // RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -nogpulib -target amdgcn-amd-amdhsa-opencl -mcpu=…
5 …HECK-DAG: ![[FILEVAR0:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, …
6 // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR0]], expr: !DIExpression())
8 …HECK-DAG: ![[FILEVAR1:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, …
9 // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR1]], expr: !DIExpression())
11 …HECK-DAG: ![[FILEVAR2:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, …
12 // CHECK-DAG: !DIGlobalVariableExpression(var: ![[FILEVAR2]], expr: !DIExpression())
14 …HECK-DAG: ![[FILEVAR3:[0-9]+]] = distinct !DIGlobalVariable(name: "FileVar3", scope: !{{[0-9]+}}, …
[all …]
H A Damdgpu-debug-info-pointer-address-space.cl1 // REQUIRES: amdgpu-registered-target
2 // RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -nogpulib -target amdgcn-amd-amdhsa -mcpu=fiji -o…
3 // RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -nogpulib -target amdgcn-amd-amdhsa-opencl -mcpu=…
5 // CHECK-DAG: ![[DWARF_ADDRESS_SPACE_NONE:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseT…
6 // CHECK-DAG: ![[DWARF_ADDRESS_SPACE_LOCAL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, base…
7 // CHECK-DAG: ![[DWARF_ADDRESS_SPACE_PRIVATE:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, ba…
9 // CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar0", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, l…
11 // CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar1", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, l…
13 // CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar2", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, l…
15 // CHECK-DAG: distinct !DIGlobalVariable(name: "FileVar3", scope: !{{[0-9]+}}, file: !{{[0-9]+}}, l…
[all …]
/llvm-project/llvm/test/CodeGen/X86/
H A Dlimited-prec.ll2 ; RUN: llc < %s -limit-float-precision=6 -mtriple=i686-- | FileCheck %s --check-prefix=precision6
3 ; RUN: llc < %s -limit-float-precision=12 -mtriple=i686-- | FileCheck %s --check-prefix=precision12
4 ; RUN: llc < %s -limit-float-precision=18 -mtriple=i686-- | FileCheck %s --check-prefix=precision18
7 ; precision6-LABEL: f1:
8 ; precision6: # %bb.0: # %entry
9 ; precision6-NEXT: subl $20, %esp
10 ; precision6-NEXT: flds {{[0-9]+}}(%esp)
11 ; precision6-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
12 ; precision6-NEXT: fnstcw (%esp)
13 ; precision6-NEXT: movzwl (%esp), %eax
[all …]
/llvm-project/cross-project-tests/amdgpu/
H A Dbuiltins-amdgcn-gfx12-wmma-w32.cl1 …%clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -target-feature +wavefrontsize32 -S …
12 // CHECK-GFX1200-LABEL: test_amdgcn_wmma_f32_16x16x16_f16_w32:
13 // CHECK-GFX1200: v_wmma_f32_16x16x16_f16 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0…
21 // CHECK-GFX1200-LABEL: test_amdgcn_wmma_f32_16x16x16_bf16_w32:
22 // CHECK-GFX1200: v_wmma_f32_16x16x16_bf16 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[…
30 // CHECK-GFX1200-LABEL: test_amdgcn_wmma_f16_16x16x16_f16_w32:
31 // CHECK-GFX1200: v_wmma_f16_16x16x16_f16 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0…
39 // CHECK-GFX1200-LABEL: test_amdgcn_wmma_bf16_16x16x16_bf16_w32:
40 // CHECK-GFX1200: v_wmma_bf16_16x16x16_bf16 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:…
47 // CHECK-GFX1200-LABEL: test_amdgcn_wmma_i32_16x16x16_iu8_w32:
[all …]
/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
H A Dload.ll2 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-pr…
3 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileC…
4 ; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-pr…
5 ; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileC…
6 ; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips3 < %s -asm-show-inst | FileCheck %s --check-pre…
7 ; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-pr…
8 ; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-…
9 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips,+fp64 < %s -asm-show-inst |…
10 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r5 -mattr=+fp64 < %s -asm-show-inst | FileCheck …
12 ; Test subword and word loads. We use -asm-show-inst to test that the produced
[all …]
H A Dstore.ll2 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-pr…
3 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileC…
4 ; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-pr…
5 ; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileC…
6 ; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-pre…
7 ; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-…
8 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips,+fp64 < %s -asm-show-inst |…
9 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r5 -mattr=+fp64 < %s -asm-show-inst | FileCheck …
11 ; Test subword and word stores. We use -asm-show-inst to test that the produced
14 ; NOTE: As the -asm-show-inst shows the internal numbering of instructions
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-sdiv.mir2 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -ch…
3 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -che…
4 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -c…
5 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -o - %s | FileCheck -…
6 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -o - %s | FileCheck -…
8 ---
11 bb.0:
14 ; GFX6-LABEL: name: test_sdiv_s32
16 ; GFX6-NEXT: {{ $}}
17 ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
[all …]
H A Dlegalize-srem.mir2 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -ch…
3 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -chec…
4 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -ch…
5 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -o - %s | FileCheck -c…
6 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -o - %s | FileCheck -c…
8 ---
11 bb.0:
14 ; GFX6-LABEL: name: test_srem_s32
16 ; GFX6-NEXT: {{ $}}
17 ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
[all …]
H A Dlegalize-urem.mir2 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -ch…
3 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -chec…
4 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -ch…
5 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -o - %s | FileCheck -c…
6 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -o - %s | FileCheck -c…
8 ---
11 bb.0:
14 ; GFX6-LABEL: name: test_urem_s32
16 ; GFX6-NEXT: {{ $}}
17 ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
[all …]
H A Dlegalize-udiv.mir2 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -ch…
3 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -chec…
4 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -ch…
5 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -o - %s | FileCheck -c…
6 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -o - %s | FileCheck -c…
8 ---
11 bb.0:
14 ; GFX6-LABEL: name: test_udiv_s32
16 ; GFX6-NEXT: {{ $}}
17 ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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H A Dregbankselect-extract-vector-elt.mir2 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fas
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/llvm-project/clang/test/CodeGen/
H A Ddebug-info-bitfield-0-struct.c1 // RUN: %clang_cc1 -triple x86_64-unk-unk -o - -emit-llvm -debug-info-kind=limited %s | FileCheck -…
2 // RUN: %clang_cc1 -triple amdgcn-unk-unk -o - -emit-llvm -debug-info-kind=limited %s | FileCheck -…
5 …-DAG: ![[FIRST:[0-9]+]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "First", fil…
6 // BOTH-DAG: ![[FIRST_ELEMENTS]] = !{![[FIRST_X:[0-9]+]], ![[FIRST_Y:[0-9]+]]}
7 …-DAG: ![[FIRST_X]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: ![[FIRST]], file: !{{[0-…
8 …-DAG: ![[FIRST_Y]] = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: ![[FIRST]], file: !{{[0-…
9 int : 0;
15 …-DAG: ![[FIRSTDUP:[0-9]+]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "FirstDup…
16 // BOTH-DAG: ![[FIRSTDUP_ELEMENTS]] = !{![[FIRSTDUP_X:[0-9]+]], ![[FIRSTDUP_Y:[0-9]+]]}
17 …-DAG: ![[FIRSTDUP_X]] = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: ![[FIRSTDUP]], file: …
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