Lines Matching +full:0 +full:- +full:9
1 ; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma.
3 …-mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | File…
4 …-mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -verify-machineinstrs -fp-contrac…
5 …-mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -verify-machineinstrs -enable-uns…
7 ; FIXME: Remove enable-unsafe-fp-math in RUN line and add flags to IR instrs
10 …-mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee -fp-contract=fast -verify-machineinstrs < …
11 …-mtriple=amdgcn -mcpu=verde -denormal-fp-math-f32=ieee -fp-contract=fast -verify-machineinstrs < %…
13 declare i32 @llvm.amdgcn.workitem.id.x() #0
14 declare float @llvm.fabs.f32(float) #0
15 declare float @llvm.fma.f32(float, float, float) #0
16 declare float @llvm.fmuladd.f32(float, float, float) #0
18 ; (fadd (fmul x, y), z) -> (fma x, y, z)
19 ; FUNC-LABEL: {{^}}combine_to_mad_f32_0:
20 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
21 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
22 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
24 ; SI-STD: v_mac_f32_e32 [[C]], [[A]], [[B]]
26 ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
28 ; SI-DENORM-SLOWFMAF-NOT: v_fma
29 ; SI-DENORM-SLOWFMAF-NOT: v_mad
31 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
32 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
34 ; SI-DENORM: buffer_store_dword [[RESULT]]
35 ; SI-STD: buffer_store_dword [[C]]
37 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
38 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
39 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
40 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
43 %a = load volatile float, ptr addrspace(1) %gep.0
53 ; (fadd (fmul x, y), z) -> (fma x, y, z)
54 ; FUNC-LABEL: {{^}}combine_to_mad_f32_0_2use:
55 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
56 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
57 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
58 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
60 ; SI-STD-DAG: v_mac_f32_e32 [[C]], [[A]], [[B]]
61 ; SI-STD-DAG: v_mac_f32_e32 [[D]], [[A]], [[B]]
63 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], [[C]]
64 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], [[D]]
66 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
67 ; SI-DENORM-SLOWFMAF-DAG: v_add_f32_e32 [[RESULT0:v[0-9]+]], [[TMP]], [[C]]
68 ; SI-DENORM-SLOWFMAF-DAG: v_add_f32_e32 [[RESULT1:v[0-9]+]], [[TMP]], [[D]]
70 ; SI-DENORM-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 …
71 ; SI-DENORM-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 …
72 ; SI-STD-DAG: buffer_store_dword [[C]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$…
73 ; SI-STD-DAG: buffer_store_dword [[D]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 of…
76 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
77 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
78 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
79 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
80 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
81 %gep.out.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid
82 %gep.out.1 = getelementptr float, ptr addrspace(1) %gep.out.0, i32 1
84 %a = load volatile float, ptr addrspace(1) %gep.0
93 store volatile float %fma0, ptr addrspace(1) %gep.out.0
98 ; (fadd x, (fmul y, z)) -> (fma y, z, x)
99 ; FUNC-LABEL: {{^}}combine_to_mad_f32_1:
100 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
101 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
102 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
104 ; SI-STD: v_mac_f32_e32 [[C]], [[A]], [[B]]
105 ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
107 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
108 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
110 ; SI-DENORM: buffer_store_dword [[RESULT]]
111 ; SI-STD: buffer_store_dword [[C]]
113 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
114 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
115 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
116 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
119 %a = load volatile float, ptr addrspace(1) %gep.0
129 ; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
130 ; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32:
131 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
132 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
133 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
135 ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
136 ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
138 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
139 ; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
143 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
144 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
145 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
146 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
149 %a = load volatile float, ptr addrspace(1) %gep.0
159 ; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
160 ; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32_2use:
161 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
162 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
163 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
164 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
166 ; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]]
167 ; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
169 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]]
170 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
172 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
173 ; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e32 [[RESULT0:v[0-9]+]], [[TMP]], [[C]]
174 ; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e32 [[RESULT1:v[0-9]+]], [[TMP]], [[D]]
176 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
177 ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 …
180 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
181 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
182 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
183 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
184 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
185 %gep.out.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid
186 %gep.out.1 = getelementptr float, ptr addrspace(1) %gep.out.0, i32 1
188 %a = load volatile float, ptr addrspace(1) %gep.0
196 store volatile float %fma0, ptr addrspace(1) %gep.out.0
201 ; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
202 ; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32:
203 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
204 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
205 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
207 ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]]
208 ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]]
210 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
211 ; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
215 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
216 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
217 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
218 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
221 %a = load volatile float, ptr addrspace(1) %gep.0
231 ; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
232 ; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32_2use:
233 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
234 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
235 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
236 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
238 ; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]]
239 ; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]]
241 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]]
242 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]]
244 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
245 ; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e32 [[RESULT0:v[0-9]+]], [[C]], [[TMP]]
246 ; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e32 [[RESULT1:v[0-9]+]], [[D]], [[TMP]]
248 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
249 ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 …
252 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
253 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
254 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
255 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
256 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
257 %gep.out.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid
258 %gep.out.1 = getelementptr float, ptr addrspace(1) %gep.out.0, i32 1
260 %a = load volatile float, ptr addrspace(1) %gep.0
268 store volatile float %fma0, ptr addrspace(1) %gep.out.0
273 ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
274 ; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32:
275 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
276 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
277 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
279 ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], -[[B]], -[[C]]
281 ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], -[[C]]
283 ; SI-DENORM-SLOWFMAF: v_mul_f32_e64 [[TMP:v[0-9]+]], [[A]], -[[B]]
284 ; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
288 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
289 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
290 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
291 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
294 %a = load volatile float, ptr addrspace(1) %gep.0
306 ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
307 ; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_neg:
308 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
309 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
310 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
311 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
313 ; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], -[[B]], -[[C]]
314 ; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], -[[B]], -[[D]]
316 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
317 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], -[[D]]
319 ; SI-DENORM-SLOWFMAF: v_mul_f32_e64 [[TMP:v[0-9]+]], [[A]], -[[B]]
320 ; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e32 [[RESULT0:v[0-9]+]], [[TMP]], [[C]]
321 ; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e32 [[RESULT1:v[0-9]+]], [[TMP]], [[D]]
323 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
324 ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 …
327 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
328 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
329 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
330 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
331 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
332 %gep.out.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid
333 %gep.out.1 = getelementptr float, ptr addrspace(1) %gep.out.0, i32 1
335 %a = load volatile float, ptr addrspace(1) %gep.0
345 store volatile float %fma0, ptr addrspace(1) %gep.out.0
350 ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
351 ; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_mul:
352 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
353 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
354 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
355 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
357 ; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
358 ; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
360 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
361 ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
363 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
364 ; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e64 [[RESULT0:v[0-9]+]], -[[TMP]], [[C]]
365 ; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e32 [[RESULT1:v[0-9]+]], [[TMP]], [[D]]
367 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{…
368 ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 …
371 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
372 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
373 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
374 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
375 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
376 %gep.out.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid
377 %gep.out.1 = getelementptr float, ptr addrspace(1) %gep.out.0, i32 1
379 %a = load volatile float, ptr addrspace(1) %gep.0
389 store volatile float %fma0, ptr addrspace(1) %gep.out.0
394 ; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
396 ; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_0_f32:
397 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
398 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
399 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
400 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
401 ; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
403 ; SI-STD-SAFE: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
404 ; SI-STD-SAFE: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
405 ; SI-STD-SAFE: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[C]]
407 ; SI-STD-UNSAFE: v_mad_f32 [[RESULT:v[0-9]+]], [[D]], [[E]], -[[C]]
408 ; SI-STD-UNSAFE: v_mac_f32_e32 [[RESULT]], [[A]], [[B]]
410 ; SI-DENORM: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
411 ; SI-DENORM: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
412 ; SI-DENORM: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[C]]
414 ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
416 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
417 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
418 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
419 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
420 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
421 %gep.4 = getelementptr float, ptr addrspace(1) %gep.0, i32 4
424 %x = load volatile float, ptr addrspace(1) %gep.0
431 %tmp1 = call float @llvm.fma.f32(float %x, float %y, float %tmp0) #0
439 ; -> (fma (fneg y), z, (fma (fneg u), v, x))
441 ; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_1_f32:
442 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
443 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
444 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
445 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
446 ; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
448 ; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
449 ; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
450 ; SI-STD: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP1]]
452 ; SI-DENORM: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
453 ; SI-DENORM: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
454 ; SI-DENORM: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP1]]
456 ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
459 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
460 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
461 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
462 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
463 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
464 %gep.4 = getelementptr float, ptr addrspace(1) %gep.0, i32 4
467 %x = load volatile float, ptr addrspace(1) %gep.0
474 %tmp1 = call float @llvm.fma.f32(float %y, float %z, float %tmp0) #0
481 ; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
483 ; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_2_f32:
484 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
485 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
486 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
487 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
488 ; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
490 ; SI-STD-SAFE: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
491 ; SI-STD-SAFE: v_mac_f32_e32 [[TMP0]], [[A]], [[B]]
492 ; SI-STD-SAFE: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP0]], [[C]]
494 ; SI-STD-UNSAFE: v_mad_f32 [[RESULT:v[0-9]+]], [[D]], [[E]], -[[C]]
495 ; SI-STD-UNSAFE: v_mac_f32_e32 [[RESULT]], [[A]], [[B]]
497 ; SI-DENORM-FASTFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
498 ; SI-DENORM-FASTFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
499 ; SI-DENORM-FASTFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[C]]
501 ; SI-DENORM-SLOWFMAF-DAG: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
502 ; SI-DENORM-SLOWFMAF-DAG: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[A]], [[B]]
503 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP1]], [[TMP0]]
504 ; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP2]], [[C]]
506 ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
509 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
510 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
511 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
512 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
513 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
514 %gep.4 = getelementptr float, ptr addrspace(1) %gep.0, i32 4
517 %x = load volatile float, ptr addrspace(1) %gep.0
524 %tmp1 = call float @llvm.fmuladd.f32(float %x, float %y, float %tmp0) #0
532 ; -> (fmuladd (fneg y), z, (fmuladd (fneg u), v, x))
534 ; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_3_f32:
535 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
536 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
537 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
538 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
539 ; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
541 ; SI-STD-SAFE: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
542 ; SI-STD-SAFE: v_mac_f32_e32 [[TMP0]], [[B]], [[C]]
543 ; SI-STD-SAFE: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP0]]
545 ; SI-STD-UNSAFE: v_mad_f32 [[TMP:v[0-9]+]], -[[D]], [[E]], [[A]]
546 ; SI-STD-UNSAFE: v_mad_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP]]
548 ; SI-DENORM-FASTFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
549 ; SI-DENORM-FASTFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
550 ; SI-DENORM-FASTFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP1]]
552 ; SI-DENORM-SLOWFMAF-DAG: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
553 ; SI-DENORM-SLOWFMAF-DAG: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[B]], [[C]]
554 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP1]], [[TMP0]]
555 ; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP2]]
557 ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
560 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
561 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
562 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
563 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
564 %gep.3 = getelementptr float, ptr addrspace(1) %gep.0, i32 3
565 %gep.4 = getelementptr float, ptr addrspace(1) %gep.0, i32 4
568 %x = load volatile float, ptr addrspace(1) %gep.0
576 %tmp1 = call nsz float @llvm.fmuladd.f32(float %y, float %z, float %tmp0) #0
583 attributes #0 = { nounwind readnone }