xref: /llvm-project/llvm/test/CodeGen/Mips/llvm-ir/load.ll (revision 8663926a544602932d299dda435ed1ef70a05f48) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
3; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
4; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
5; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
6; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips3 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS3
7; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64
8; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
9; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips,+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MMR5FP64
10; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r5 -mattr=+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R5FP643
11
12; Test subword and word loads. We use -asm-show-inst to test that the produced
13; instructions match the expected ISA.
14
15; NOTE: As the -asm-show-inst shows the internal numbering of instructions
16;       and registers, these numbers have been replaced with wildcard regexes.
17
18@a = common global i8 0, align 4
19@b = common global i16 0, align 4
20@c = common global i32 0, align 4
21@d = common global i64 0, align 8
22@e = common global float 0.0, align 4
23@f = common global double 0.0, align 8
24
25define i8 @f1() {
26; MIPS32-LABEL: f1:
27; MIPS32:       # %bb.0: # %entry
28; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
29; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
30; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
31; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
32; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
33; MIPS32-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
34; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
35; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
36; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
37;
38; MMR3-LABEL: f1:
39; MMR3:       # %bb.0: # %entry
40; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
41; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
42; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
43; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
44; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
45; MMR3-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
46; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
47; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
48; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
49;
50; MIPS32R6-LABEL: f1:
51; MIPS32R6:       # %bb.0: # %entry
52; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
53; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
54; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
55; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
56; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
57; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
58; MIPS32R6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
59; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
60; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
61; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
62;
63; MMR6-LABEL: f1:
64; MMR6:       # %bb.0: # %entry
65; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
66; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
67; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
68; MMR6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
69; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
70; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
71; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
72; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
73; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
74;
75; MIPS3-LABEL: f1:
76; MIPS3:       # %bb.0: # %entry
77; MIPS3-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
78; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
79; MIPS3-NEXT:    # <MCOperand Expr:(%highest(a))>>
80; MIPS3-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
81; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
82; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
83; MIPS3-NEXT:    # <MCOperand Expr:(%higher(a))>>
84; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
85; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
86; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
87; MIPS3-NEXT:    # <MCOperand Imm:16>>
88; MIPS3-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
89; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
90; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
91; MIPS3-NEXT:    # <MCOperand Expr:(%hi(a))>>
92; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
93; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
94; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
95; MIPS3-NEXT:    # <MCOperand Imm:16>>
96; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
97; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
98; MIPS3-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
99; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
100; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
101; MIPS3-NEXT:    # <MCOperand Expr:(%lo(a))>>
102;
103; MIPS64-LABEL: f1:
104; MIPS64:       # %bb.0: # %entry
105; MIPS64-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
106; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
107; MIPS64-NEXT:    # <MCOperand Expr:(%highest(a))>>
108; MIPS64-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
109; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
110; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
111; MIPS64-NEXT:    # <MCOperand Expr:(%higher(a))>>
112; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
113; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
114; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
115; MIPS64-NEXT:    # <MCOperand Imm:16>>
116; MIPS64-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
117; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
118; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
119; MIPS64-NEXT:    # <MCOperand Expr:(%hi(a))>>
120; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
121; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
122; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
123; MIPS64-NEXT:    # <MCOperand Imm:16>>
124; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
125; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
126; MIPS64-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
127; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
128; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
129; MIPS64-NEXT:    # <MCOperand Expr:(%lo(a))>>
130;
131; MIPS64R6-LABEL: f1:
132; MIPS64R6:       # %bb.0: # %entry
133; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
134; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
135; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
136; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
137; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
138; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
139; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
140; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
141; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
142; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
143; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
144; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
145; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
146; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
147; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
148; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
149; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
150; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
151; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
152; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
153; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
154; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
155; MIPS64R6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
156; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
157; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
158; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
159;
160; MMR5FP64-LABEL: f1:
161; MMR5FP64:       # %bb.0: # %entry
162; MMR5FP64-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
163; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
164; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(a))>>
165; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
166; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
167; MMR5FP64-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
168; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
169; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
170; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(a))>>
171;
172; MIPS32R5FP643-LABEL: f1:
173; MIPS32R5FP643:       # %bb.0: # %entry
174; MIPS32R5FP643-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
175; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
176; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(a))>>
177; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
178; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
179; MIPS32R5FP643-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
180; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
181; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
182; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(a))>>
183entry:
184  %0 = load i8, ptr @a
185  ret i8 %0
186}
187
188define i32 @f2() {
189; MIPS32-LABEL: f2:
190; MIPS32:       # %bb.0: # %entry
191; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
192; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
193; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
194; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
195; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
196; MIPS32-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
197; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
198; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
199; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
200;
201; MMR3-LABEL: f2:
202; MMR3:       # %bb.0: # %entry
203; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
204; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
205; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
206; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
207; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
208; MMR3-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
209; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
210; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
211; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
212;
213; MIPS32R6-LABEL: f2:
214; MIPS32R6:       # %bb.0: # %entry
215; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
216; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
217; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
218; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
219; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
220; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
221; MIPS32R6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
222; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
223; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
224; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
225;
226; MMR6-LABEL: f2:
227; MMR6:       # %bb.0: # %entry
228; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
229; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
230; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
231; MMR6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
232; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
233; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
234; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
235; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
236; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
237;
238; MIPS3-LABEL: f2:
239; MIPS3:       # %bb.0: # %entry
240; MIPS3-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
241; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
242; MIPS3-NEXT:    # <MCOperand Expr:(%highest(a))>>
243; MIPS3-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
244; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
245; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
246; MIPS3-NEXT:    # <MCOperand Expr:(%higher(a))>>
247; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
248; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
249; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
250; MIPS3-NEXT:    # <MCOperand Imm:16>>
251; MIPS3-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
252; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
253; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
254; MIPS3-NEXT:    # <MCOperand Expr:(%hi(a))>>
255; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
256; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
257; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
258; MIPS3-NEXT:    # <MCOperand Imm:16>>
259; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
260; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
261; MIPS3-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
262; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
263; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
264; MIPS3-NEXT:    # <MCOperand Expr:(%lo(a))>>
265;
266; MIPS64-LABEL: f2:
267; MIPS64:       # %bb.0: # %entry
268; MIPS64-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
269; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
270; MIPS64-NEXT:    # <MCOperand Expr:(%highest(a))>>
271; MIPS64-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
272; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
273; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
274; MIPS64-NEXT:    # <MCOperand Expr:(%higher(a))>>
275; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
276; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
277; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
278; MIPS64-NEXT:    # <MCOperand Imm:16>>
279; MIPS64-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
280; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
281; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
282; MIPS64-NEXT:    # <MCOperand Expr:(%hi(a))>>
283; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
284; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
285; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
286; MIPS64-NEXT:    # <MCOperand Imm:16>>
287; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
288; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
289; MIPS64-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
290; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
291; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
292; MIPS64-NEXT:    # <MCOperand Expr:(%lo(a))>>
293;
294; MIPS64R6-LABEL: f2:
295; MIPS64R6:       # %bb.0: # %entry
296; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
297; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
298; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
299; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
300; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
301; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
302; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
303; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
304; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
305; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
306; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
307; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
308; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
309; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
310; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
311; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
312; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
313; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
314; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
315; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
316; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
317; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
318; MIPS64R6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
319; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
320; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
321; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
322;
323; MMR5FP64-LABEL: f2:
324; MMR5FP64:       # %bb.0: # %entry
325; MMR5FP64-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
326; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
327; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(a))>>
328; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
329; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
330; MMR5FP64-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
331; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
332; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
333; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(a))>>
334;
335; MIPS32R5FP643-LABEL: f2:
336; MIPS32R5FP643:       # %bb.0: # %entry
337; MIPS32R5FP643-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
338; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
339; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(a))>>
340; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
341; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
342; MIPS32R5FP643-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
343; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
344; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
345; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(a))>>
346entry:
347  %0 = load i8, ptr @a
348  %1 = sext i8 %0 to i32
349  ret i32 %1
350}
351
352define i16 @f3() {
353; MIPS32-LABEL: f3:
354; MIPS32:       # %bb.0: # %entry
355; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
356; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
357; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
358; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
359; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
360; MIPS32-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
361; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
362; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
363; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
364;
365; MMR3-LABEL: f3:
366; MMR3:       # %bb.0: # %entry
367; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
368; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
369; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
370; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
371; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
372; MMR3-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
373; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
374; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
375; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
376;
377; MIPS32R6-LABEL: f3:
378; MIPS32R6:       # %bb.0: # %entry
379; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
380; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
381; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
382; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
383; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
384; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
385; MIPS32R6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
386; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
387; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
388; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
389;
390; MMR6-LABEL: f3:
391; MMR6:       # %bb.0: # %entry
392; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
393; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
394; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
395; MMR6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
396; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
397; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
398; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
399; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
400; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
401;
402; MIPS3-LABEL: f3:
403; MIPS3:       # %bb.0: # %entry
404; MIPS3-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
405; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
406; MIPS3-NEXT:    # <MCOperand Expr:(%highest(b))>>
407; MIPS3-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
408; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
409; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
410; MIPS3-NEXT:    # <MCOperand Expr:(%higher(b))>>
411; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
412; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
413; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
414; MIPS3-NEXT:    # <MCOperand Imm:16>>
415; MIPS3-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
416; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
417; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
418; MIPS3-NEXT:    # <MCOperand Expr:(%hi(b))>>
419; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
420; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
421; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
422; MIPS3-NEXT:    # <MCOperand Imm:16>>
423; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
424; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
425; MIPS3-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
426; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
427; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
428; MIPS3-NEXT:    # <MCOperand Expr:(%lo(b))>>
429;
430; MIPS64-LABEL: f3:
431; MIPS64:       # %bb.0: # %entry
432; MIPS64-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
433; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
434; MIPS64-NEXT:    # <MCOperand Expr:(%highest(b))>>
435; MIPS64-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
436; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
437; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
438; MIPS64-NEXT:    # <MCOperand Expr:(%higher(b))>>
439; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
440; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
441; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
442; MIPS64-NEXT:    # <MCOperand Imm:16>>
443; MIPS64-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
444; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
445; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
446; MIPS64-NEXT:    # <MCOperand Expr:(%hi(b))>>
447; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
448; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
449; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
450; MIPS64-NEXT:    # <MCOperand Imm:16>>
451; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
452; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
453; MIPS64-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
454; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
455; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
456; MIPS64-NEXT:    # <MCOperand Expr:(%lo(b))>>
457;
458; MIPS64R6-LABEL: f3:
459; MIPS64R6:       # %bb.0: # %entry
460; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
461; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
462; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
463; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
464; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
465; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
466; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
467; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
468; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
469; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
470; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
471; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
472; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
473; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
474; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
475; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
476; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
477; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
478; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
479; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
480; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
481; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
482; MIPS64R6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
483; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
484; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
485; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
486;
487; MMR5FP64-LABEL: f3:
488; MMR5FP64:       # %bb.0: # %entry
489; MMR5FP64-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
490; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
491; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(b))>>
492; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
493; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
494; MMR5FP64-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
495; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
496; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
497; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(b))>>
498;
499; MIPS32R5FP643-LABEL: f3:
500; MIPS32R5FP643:       # %bb.0: # %entry
501; MIPS32R5FP643-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
502; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
503; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(b))>>
504; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
505; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
506; MIPS32R5FP643-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
507; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
508; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
509; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(b))>>
510entry:
511  %0 = load i16, ptr @b
512  ret i16 %0
513}
514
515define i32 @f4() {
516; MIPS32-LABEL: f4:
517; MIPS32:       # %bb.0: # %entry
518; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
519; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
520; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
521; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
522; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
523; MIPS32-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
524; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
525; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
526; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
527;
528; MMR3-LABEL: f4:
529; MMR3:       # %bb.0: # %entry
530; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
531; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
532; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
533; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
534; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
535; MMR3-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
536; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
537; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
538; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
539;
540; MIPS32R6-LABEL: f4:
541; MIPS32R6:       # %bb.0: # %entry
542; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
543; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
544; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
545; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
546; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
547; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
548; MIPS32R6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
549; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
550; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
551; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
552;
553; MMR6-LABEL: f4:
554; MMR6:       # %bb.0: # %entry
555; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
556; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
557; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
558; MMR6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
559; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
560; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
561; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
562; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
563; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
564;
565; MIPS3-LABEL: f4:
566; MIPS3:       # %bb.0: # %entry
567; MIPS3-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
568; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
569; MIPS3-NEXT:    # <MCOperand Expr:(%highest(b))>>
570; MIPS3-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
571; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
572; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
573; MIPS3-NEXT:    # <MCOperand Expr:(%higher(b))>>
574; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
575; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
576; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
577; MIPS3-NEXT:    # <MCOperand Imm:16>>
578; MIPS3-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
579; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
580; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
581; MIPS3-NEXT:    # <MCOperand Expr:(%hi(b))>>
582; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
583; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
584; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
585; MIPS3-NEXT:    # <MCOperand Imm:16>>
586; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
587; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
588; MIPS3-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
589; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
590; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
591; MIPS3-NEXT:    # <MCOperand Expr:(%lo(b))>>
592;
593; MIPS64-LABEL: f4:
594; MIPS64:       # %bb.0: # %entry
595; MIPS64-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
596; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
597; MIPS64-NEXT:    # <MCOperand Expr:(%highest(b))>>
598; MIPS64-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
599; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
600; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
601; MIPS64-NEXT:    # <MCOperand Expr:(%higher(b))>>
602; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
603; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
604; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
605; MIPS64-NEXT:    # <MCOperand Imm:16>>
606; MIPS64-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
607; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
608; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
609; MIPS64-NEXT:    # <MCOperand Expr:(%hi(b))>>
610; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
611; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
612; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
613; MIPS64-NEXT:    # <MCOperand Imm:16>>
614; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
615; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
616; MIPS64-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
617; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
618; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
619; MIPS64-NEXT:    # <MCOperand Expr:(%lo(b))>>
620;
621; MIPS64R6-LABEL: f4:
622; MIPS64R6:       # %bb.0: # %entry
623; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
624; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
625; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
626; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
627; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
628; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
629; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
630; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
631; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
632; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
633; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
634; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
635; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
636; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
637; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
638; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
639; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
640; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
641; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
642; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
643; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
644; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
645; MIPS64R6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
646; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
647; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
648; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
649;
650; MMR5FP64-LABEL: f4:
651; MMR5FP64:       # %bb.0: # %entry
652; MMR5FP64-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
653; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
654; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(b))>>
655; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
656; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
657; MMR5FP64-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
658; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
659; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
660; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(b))>>
661;
662; MIPS32R5FP643-LABEL: f4:
663; MIPS32R5FP643:       # %bb.0: # %entry
664; MIPS32R5FP643-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
665; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
666; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(b))>>
667; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
668; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
669; MIPS32R5FP643-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
670; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
671; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
672; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(b))>>
673entry:
674  %0 = load i16, ptr @b
675  %1 = sext i16 %0 to i32
676  ret i32 %1
677}
678
679define i32 @f5() {
680; MIPS32-LABEL: f5:
681; MIPS32:       # %bb.0: # %entry
682; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
683; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
684; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
685; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
686; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
687; MIPS32-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
688; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
689; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
690; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
691;
692; MMR3-LABEL: f5:
693; MMR3:       # %bb.0: # %entry
694; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
695; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
696; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
697; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
698; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
699; MMR3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
700; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
701; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
702; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
703;
704; MIPS32R6-LABEL: f5:
705; MIPS32R6:       # %bb.0: # %entry
706; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
707; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
708; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
709; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
710; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
711; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
712; MIPS32R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
713; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
714; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
715; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
716;
717; MMR6-LABEL: f5:
718; MMR6:       # %bb.0: # %entry
719; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
720; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
721; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
722; MMR6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
723; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
724; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
725; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
726; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
727; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
728;
729; MIPS3-LABEL: f5:
730; MIPS3:       # %bb.0: # %entry
731; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
732; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
733; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
734; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
735; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
736; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
737; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
738; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
739; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
740; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
741; MIPS3-NEXT:    # <MCOperand Imm:16>>
742; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
743; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
744; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
745; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
746; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
747; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
748; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
749; MIPS3-NEXT:    # <MCOperand Imm:16>>
750; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
751; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
752; MIPS3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
753; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
754; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
755; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
756;
757; MIPS64-LABEL: f5:
758; MIPS64:       # %bb.0: # %entry
759; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
760; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
761; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
762; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
763; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
764; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
765; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
766; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
767; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
768; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
769; MIPS64-NEXT:    # <MCOperand Imm:16>>
770; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
771; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
772; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
773; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
774; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
775; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
776; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
777; MIPS64-NEXT:    # <MCOperand Imm:16>>
778; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
779; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
780; MIPS64-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
781; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
782; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
783; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
784;
785; MIPS64R6-LABEL: f5:
786; MIPS64R6:       # %bb.0: # %entry
787; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
788; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
789; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
790; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
791; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
792; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
793; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
794; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
795; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
796; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
797; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
798; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
799; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
800; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
801; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
802; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
803; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
804; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
805; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
806; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
807; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
808; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
809; MIPS64R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
810; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
811; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
812; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
813;
814; MMR5FP64-LABEL: f5:
815; MMR5FP64:       # %bb.0: # %entry
816; MMR5FP64-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
817; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
818; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(c))>>
819; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
820; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
821; MMR5FP64-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
822; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
823; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
824; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(c))>>
825;
826; MIPS32R5FP643-LABEL: f5:
827; MIPS32R5FP643:       # %bb.0: # %entry
828; MIPS32R5FP643-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
829; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
830; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(c))>>
831; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
832; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
833; MIPS32R5FP643-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
834; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
835; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
836; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(c))>>
837entry:
838  %0 = load i32, ptr @c
839  ret i32 %0
840}
841
842define i64 @f6() {
843; MIPS32-LABEL: f6:
844; MIPS32:       # %bb.0: # %entry
845; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
846; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
847; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
848; MIPS32-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
849; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
850; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
851; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
852; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
853; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
854; MIPS32-NEXT:    addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
855; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
856; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
857; MIPS32-NEXT:    # <MCOperand Imm:0>>
858;
859; MMR3-LABEL: f6:
860; MMR3:       # %bb.0: # %entry
861; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
862; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
863; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
864; MMR3-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
865; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
866; MMR3-NEXT:    # <MCOperand Imm:0>>
867; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
868; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
869; MMR3-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
870; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
871; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
872; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
873;
874; MIPS32R6-LABEL: f6:
875; MIPS32R6:       # %bb.0: # %entry
876; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
877; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
878; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
879; MIPS32R6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
880; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
881; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
882; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
883; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
884; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
885; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
886; MIPS32R6-NEXT:    addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
887; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
888; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
889; MIPS32R6-NEXT:    # <MCOperand Imm:0>>
890;
891; MMR6-LABEL: f6:
892; MMR6:       # %bb.0: # %entry
893; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
894; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
895; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
896; MMR6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
897; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
898; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
899; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
900; MMR6-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
901; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
902; MMR6-NEXT:    # <MCOperand Imm:0>>
903; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
904; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
905;
906; MIPS3-LABEL: f6:
907; MIPS3:       # %bb.0: # %entry
908; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
909; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
910; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
911; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
912; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
913; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
914; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
915; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
916; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
917; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
918; MIPS3-NEXT:    # <MCOperand Imm:16>>
919; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
920; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
921; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
922; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
923; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
924; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
925; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
926; MIPS3-NEXT:    # <MCOperand Imm:16>>
927; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
928; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
929; MIPS3-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
930; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
931; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
932; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
933;
934; MIPS64-LABEL: f6:
935; MIPS64:       # %bb.0: # %entry
936; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
937; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
938; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
939; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
940; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
941; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
942; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
943; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
944; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
945; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
946; MIPS64-NEXT:    # <MCOperand Imm:16>>
947; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
948; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
949; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
950; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
951; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
952; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
953; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
954; MIPS64-NEXT:    # <MCOperand Imm:16>>
955; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
956; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
957; MIPS64-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
958; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
959; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
960; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
961;
962; MIPS64R6-LABEL: f6:
963; MIPS64R6:       # %bb.0: # %entry
964; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
965; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
966; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
967; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
968; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
969; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
970; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
971; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
972; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
973; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
974; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
975; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
976; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
977; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
978; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
979; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
980; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
981; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
982; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
983; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
984; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
985; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
986; MIPS64R6-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
987; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
988; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
989; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
990;
991; MMR5FP64-LABEL: f6:
992; MMR5FP64:       # %bb.0: # %entry
993; MMR5FP64-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
994; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
995; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(c))>>
996; MMR5FP64-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
997; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
998; MMR5FP64-NEXT:    # <MCOperand Imm:0>>
999; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
1000; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1001; MMR5FP64-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
1002; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1003; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1004; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(c))>>
1005;
1006; MIPS32R5FP643-LABEL: f6:
1007; MIPS32R5FP643:       # %bb.0: # %entry
1008; MIPS32R5FP643-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
1009; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1010; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(c))>>
1011; MIPS32R5FP643-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
1012; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1013; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1014; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(c))>>
1015; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1016; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1017; MIPS32R5FP643-NEXT:    addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
1018; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1019; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1020; MIPS32R5FP643-NEXT:    # <MCOperand Imm:0>>
1021entry:
1022  %0 = load i32, ptr @c
1023  %1 = zext i32 %0 to i64
1024  ret i64 %1
1025}
1026
1027define i64 @f7() {
1028; MIPS32-LABEL: f7:
1029; MIPS32:       # %bb.0: # %entry
1030; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
1031; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1032; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
1033; MIPS32-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
1034; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1035; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1036; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
1037; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1038; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1039; MIPS32-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
1040; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1041; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1042; MIPS32-NEXT:    # <MCOperand Imm:31>>
1043;
1044; MMR3-LABEL: f7:
1045; MMR3:       # %bb.0: # %entry
1046; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
1047; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1048; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
1049; MMR3-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
1050; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1051; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1052; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
1053; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
1054; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1055; MMR3-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
1056; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1057; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1058; MMR3-NEXT:    # <MCOperand Imm:31>>
1059;
1060; MIPS32R6-LABEL: f7:
1061; MIPS32R6:       # %bb.0: # %entry
1062; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
1063; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1064; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
1065; MIPS32R6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
1066; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1067; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1068; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
1069; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
1070; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1071; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1072; MIPS32R6-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
1073; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1074; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1075; MIPS32R6-NEXT:    # <MCOperand Imm:31>>
1076;
1077; MMR6-LABEL: f7:
1078; MMR6:       # %bb.0: # %entry
1079; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
1080; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1081; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
1082; MMR6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
1083; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1084; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1085; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
1086; MMR6-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
1087; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1088; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1089; MMR6-NEXT:    # <MCOperand Imm:31>>
1090; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
1091; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1092;
1093; MIPS3-LABEL: f7:
1094; MIPS3:       # %bb.0: # %entry
1095; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
1096; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1097; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
1098; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
1099; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1100; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1101; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
1102; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1103; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1104; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1105; MIPS3-NEXT:    # <MCOperand Imm:16>>
1106; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
1107; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1108; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1109; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
1110; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1111; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1112; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1113; MIPS3-NEXT:    # <MCOperand Imm:16>>
1114; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1115; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1116; MIPS3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
1117; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1118; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1119; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
1120;
1121; MIPS64-LABEL: f7:
1122; MIPS64:       # %bb.0: # %entry
1123; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
1124; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1125; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
1126; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
1127; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1128; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1129; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
1130; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1131; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1132; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1133; MIPS64-NEXT:    # <MCOperand Imm:16>>
1134; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
1135; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1136; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1137; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
1138; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1139; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1140; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1141; MIPS64-NEXT:    # <MCOperand Imm:16>>
1142; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1143; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1144; MIPS64-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
1145; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1146; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1147; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
1148;
1149; MIPS64R6-LABEL: f7:
1150; MIPS64R6:       # %bb.0: # %entry
1151; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
1152; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1153; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
1154; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
1155; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1156; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1157; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
1158; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1159; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1160; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1161; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
1162; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
1163; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1164; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1165; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
1166; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1167; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1168; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1169; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
1170; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
1171; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1172; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1173; MIPS64R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
1174; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1175; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1176; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
1177;
1178; MMR5FP64-LABEL: f7:
1179; MMR5FP64:       # %bb.0: # %entry
1180; MMR5FP64-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
1181; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1182; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(c))>>
1183; MMR5FP64-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
1184; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1185; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1186; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(c))>>
1187; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
1188; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1189; MMR5FP64-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
1190; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1191; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1192; MMR5FP64-NEXT:    # <MCOperand Imm:31>>
1193;
1194; MIPS32R5FP643-LABEL: f7:
1195; MIPS32R5FP643:       # %bb.0: # %entry
1196; MIPS32R5FP643-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
1197; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1198; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(c))>>
1199; MIPS32R5FP643-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
1200; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1201; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1202; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(c))>>
1203; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1204; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1205; MIPS32R5FP643-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
1206; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1207; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1208; MIPS32R5FP643-NEXT:    # <MCOperand Imm:31>>
1209entry:
1210  %0 = load i32, ptr @c
1211  %1 = sext i32 %0 to i64
1212  ret i64 %1
1213}
1214
1215define float @f8() {
1216; MIPS32-LABEL: f8:
1217; MIPS32:       # %bb.0: # %entry
1218; MIPS32-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
1219; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1220; MIPS32-NEXT:    # <MCOperand Expr:(%hi(e))>>
1221; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1222; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1223; MIPS32-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1224; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1225; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1226; MIPS32-NEXT:    # <MCOperand Expr:(%lo(e))>>
1227;
1228; MMR3-LABEL: f8:
1229; MMR3:       # %bb.0: # %entry
1230; MMR3-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
1231; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1232; MMR3-NEXT:    # <MCOperand Expr:(%hi(e))>>
1233; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
1234; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1235; MMR3-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
1236; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1237; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1238; MMR3-NEXT:    # <MCOperand Expr:(%lo(e))>>
1239;
1240; MIPS32R6-LABEL: f8:
1241; MIPS32R6:       # %bb.0: # %entry
1242; MIPS32R6-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
1243; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1244; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(e))>>
1245; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
1246; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1247; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1248; MIPS32R6-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1249; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1250; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1251; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(e))>>
1252;
1253; MMR6-LABEL: f8:
1254; MMR6:       # %bb.0: # %entry
1255; MMR6-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
1256; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1257; MMR6-NEXT:    # <MCOperand Expr:(%hi(e))>>
1258; MMR6-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
1259; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1260; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1261; MMR6-NEXT:    # <MCOperand Expr:(%lo(e))>>
1262; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
1263; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1264;
1265; MIPS3-LABEL: f8:
1266; MIPS3:       # %bb.0: # %entry
1267; MIPS3-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
1268; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1269; MIPS3-NEXT:    # <MCOperand Expr:(%highest(e))>>
1270; MIPS3-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
1271; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1272; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1273; MIPS3-NEXT:    # <MCOperand Expr:(%higher(e))>>
1274; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1275; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1276; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1277; MIPS3-NEXT:    # <MCOperand Imm:16>>
1278; MIPS3-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
1279; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1280; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1281; MIPS3-NEXT:    # <MCOperand Expr:(%hi(e))>>
1282; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1283; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1284; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1285; MIPS3-NEXT:    # <MCOperand Imm:16>>
1286; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1287; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1288; MIPS3-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1289; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1290; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1291; MIPS3-NEXT:    # <MCOperand Expr:(%lo(e))>>
1292;
1293; MIPS64-LABEL: f8:
1294; MIPS64:       # %bb.0: # %entry
1295; MIPS64-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
1296; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1297; MIPS64-NEXT:    # <MCOperand Expr:(%highest(e))>>
1298; MIPS64-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
1299; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1300; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1301; MIPS64-NEXT:    # <MCOperand Expr:(%higher(e))>>
1302; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1303; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1304; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1305; MIPS64-NEXT:    # <MCOperand Imm:16>>
1306; MIPS64-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
1307; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1308; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1309; MIPS64-NEXT:    # <MCOperand Expr:(%hi(e))>>
1310; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1311; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1312; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1313; MIPS64-NEXT:    # <MCOperand Imm:16>>
1314; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1315; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1316; MIPS64-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1317; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1318; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1319; MIPS64-NEXT:    # <MCOperand Expr:(%lo(e))>>
1320;
1321; MIPS64R6-LABEL: f8:
1322; MIPS64R6:       # %bb.0: # %entry
1323; MIPS64R6-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
1324; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1325; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(e))>>
1326; MIPS64R6-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
1327; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1328; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1329; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(e))>>
1330; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1331; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1332; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1333; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
1334; MIPS64R6-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
1335; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1336; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1337; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(e))>>
1338; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1339; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1340; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1341; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
1342; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
1343; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1344; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1345; MIPS64R6-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1346; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1347; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1348; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(e))>>
1349;
1350; MMR5FP64-LABEL: f8:
1351; MMR5FP64:       # %bb.0: # %entry
1352; MMR5FP64-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
1353; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1354; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(e))>>
1355; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
1356; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1357; MMR5FP64-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
1358; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1359; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1360; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(e))>>
1361;
1362; MIPS32R5FP643-LABEL: f8:
1363; MIPS32R5FP643:       # %bb.0: # %entry
1364; MIPS32R5FP643-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
1365; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1366; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(e))>>
1367; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1368; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1369; MIPS32R5FP643-NEXT:    lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1370; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1371; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1372; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(e))>>
1373entry:
1374  %0 = load float, ptr @e
1375  ret float %0
1376}
1377
1378define double @f9() {
1379; MIPS32-LABEL: f9:
1380; MIPS32:       # %bb.0: # %entry
1381; MIPS32-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
1382; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1383; MIPS32-NEXT:    # <MCOperand Expr:(%hi(f))>>
1384; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1385; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1386; MIPS32-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1
1387; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1388; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1389; MIPS32-NEXT:    # <MCOperand Expr:(%lo(f))>>
1390;
1391; MMR3-LABEL: f9:
1392; MMR3:       # %bb.0: # %entry
1393; MMR3-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
1394; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1395; MMR3-NEXT:    # <MCOperand Expr:(%hi(f))>>
1396; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
1397; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1398; MMR3-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_MM_D32
1399; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1400; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1401; MMR3-NEXT:    # <MCOperand Expr:(%lo(f))>>
1402;
1403; MIPS32R6-LABEL: f9:
1404; MIPS32R6:       # %bb.0: # %entry
1405; MIPS32R6-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
1406; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1407; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(f))>>
1408; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
1409; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1410; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1411; MIPS32R6-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1412; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1413; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1414; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(f))>>
1415;
1416; MMR6-LABEL: f9:
1417; MMR6:       # %bb.0: # %entry
1418; MMR6-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
1419; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1420; MMR6-NEXT:    # <MCOperand Expr:(%hi(f))>>
1421; MMR6-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_D64_MMR6
1422; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1423; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1424; MMR6-NEXT:    # <MCOperand Expr:(%lo(f))>>
1425; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
1426; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1427;
1428; MIPS3-LABEL: f9:
1429; MIPS3:       # %bb.0: # %entry
1430; MIPS3-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
1431; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1432; MIPS3-NEXT:    # <MCOperand Expr:(%highest(f))>>
1433; MIPS3-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
1434; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1435; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1436; MIPS3-NEXT:    # <MCOperand Expr:(%higher(f))>>
1437; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1438; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1439; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1440; MIPS3-NEXT:    # <MCOperand Imm:16>>
1441; MIPS3-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
1442; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1443; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1444; MIPS3-NEXT:    # <MCOperand Expr:(%hi(f))>>
1445; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1446; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1447; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1448; MIPS3-NEXT:    # <MCOperand Imm:16>>
1449; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1450; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1451; MIPS3-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1452; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1453; MIPS3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1454; MIPS3-NEXT:    # <MCOperand Expr:(%lo(f))>>
1455;
1456; MIPS64-LABEL: f9:
1457; MIPS64:       # %bb.0: # %entry
1458; MIPS64-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
1459; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1460; MIPS64-NEXT:    # <MCOperand Expr:(%highest(f))>>
1461; MIPS64-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
1462; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1463; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1464; MIPS64-NEXT:    # <MCOperand Expr:(%higher(f))>>
1465; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1466; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1467; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1468; MIPS64-NEXT:    # <MCOperand Imm:16>>
1469; MIPS64-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
1470; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1471; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1472; MIPS64-NEXT:    # <MCOperand Expr:(%hi(f))>>
1473; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1474; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1475; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1476; MIPS64-NEXT:    # <MCOperand Imm:16>>
1477; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1478; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1479; MIPS64-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1480; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1481; MIPS64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1482; MIPS64-NEXT:    # <MCOperand Expr:(%lo(f))>>
1483;
1484; MIPS64R6-LABEL: f9:
1485; MIPS64R6:       # %bb.0: # %entry
1486; MIPS64R6-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
1487; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1488; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(f))>>
1489; MIPS64R6-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
1490; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1491; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1492; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(f))>>
1493; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1494; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1495; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1496; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
1497; MIPS64R6-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
1498; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1499; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1500; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(f))>>
1501; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1502; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1503; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1504; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
1505; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
1506; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1507; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1508; MIPS64R6-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1509; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1510; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1511; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(f))>>
1512;
1513; MMR5FP64-LABEL: f9:
1514; MMR5FP64:       # %bb.0: # %entry
1515; MMR5FP64-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
1516; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1517; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(f))>>
1518; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
1519; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1520; MMR5FP64-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_MM_D64
1521; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1522; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1523; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(f))>>
1524;
1525; MIPS32R5FP643-LABEL: f9:
1526; MIPS32R5FP643:       # %bb.0: # %entry
1527; MIPS32R5FP643-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
1528; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1529; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(f))>>
1530; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
1531; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
1532; MIPS32R5FP643-NEXT:    ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1533; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1534; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
1535; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(f))>>
1536entry:
1537  %0 = load double, ptr @f
1538  ret double %0
1539}
1540