xref: /llvm-project/llvm/test/CodeGen/Mips/llvm-ir/store.ll (revision 8663926a544602932d299dda435ed1ef70a05f48) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
3; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
4; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
5; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
6; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS4
7; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
8; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips,+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MMR5FP64
9; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r5 -mattr=+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R5FP643
10
11; Test subword and word stores. We use -asm-show-inst to test that the produced
12; instructions match the expected ISA.
13
14; NOTE: As the -asm-show-inst shows the internal numbering of instructions
15;       and registers, these numbers have been replaced with wildcard regexes.
16
17@a = common global i8 0, align 4
18@b = common global i16 0, align 4
19@c = common global i32 0, align 4
20@d = common global i64 0, align 8
21@e = common global float 0.0, align 4
22@f = common global double 0.0, align 8
23
24define void @f1(i8 %a) {
25; MIPS32-LABEL: f1:
26; MIPS32:       # %bb.0:
27; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
28; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
29; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
30; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
31; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
32; MIPS32-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
33; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
34; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
35; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
36;
37; MMR3-LABEL: f1:
38; MMR3:       # %bb.0:
39; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
40; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
41; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
42; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
43; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
44; MMR3-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
45; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
46; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
47; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
48;
49; MIPS32R6-LABEL: f1:
50; MIPS32R6:       # %bb.0:
51; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
52; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
53; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
54; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
55; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
56; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
57; MIPS32R6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
58; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
59; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
60; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
61;
62; MMR6-LABEL: f1:
63; MMR6:       # %bb.0:
64; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
65; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
66; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
67; MMR6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
68; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
69; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
70; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
71; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
72; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
73;
74; MIPS4-LABEL: f1:
75; MIPS4:       # %bb.0:
76; MIPS4-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
77; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
78; MIPS4-NEXT:    # <MCOperand Expr:(%highest(a))>>
79; MIPS4-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
80; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
81; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
82; MIPS4-NEXT:    # <MCOperand Expr:(%higher(a))>>
83; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
84; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
85; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
86; MIPS4-NEXT:    # <MCOperand Imm:16>>
87; MIPS4-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
88; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
89; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
90; MIPS4-NEXT:    # <MCOperand Expr:(%hi(a))>>
91; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
92; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
93; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
94; MIPS4-NEXT:    # <MCOperand Imm:16>>
95; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
96; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
97; MIPS4-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
98; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
99; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
100; MIPS4-NEXT:    # <MCOperand Expr:(%lo(a))>>
101;
102; MIPS64R6-LABEL: f1:
103; MIPS64R6:       # %bb.0:
104; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
105; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
106; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
107; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
108; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
109; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
110; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
111; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
112; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
113; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
114; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
115; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
116; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
117; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
118; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
119; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
120; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
121; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
122; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
123; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
124; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
125; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
126; MIPS64R6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
127; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
128; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
129; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
130;
131; MMR5FP64-LABEL: f1:
132; MMR5FP64:       # %bb.0:
133; MMR5FP64-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
134; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
135; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(a))>>
136; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
137; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
138; MMR5FP64-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
139; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
140; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
141; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(a))>>
142;
143; MIPS32R5FP643-LABEL: f1:
144; MIPS32R5FP643:       # %bb.0:
145; MIPS32R5FP643-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
146; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
147; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(a))>>
148; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
149; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
150; MIPS32R5FP643-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
151; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
152; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
153; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(a))>>
154  store i8 %a, ptr @a
155  ret void
156}
157
158define void @f2(i16 %a) {
159; MIPS32-LABEL: f2:
160; MIPS32:       # %bb.0:
161; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
162; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
163; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
164; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
165; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
166; MIPS32-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
167; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
168; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
169; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
170;
171; MMR3-LABEL: f2:
172; MMR3:       # %bb.0:
173; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
174; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
175; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
176; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
177; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
178; MMR3-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
179; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
180; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
181; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
182;
183; MIPS32R6-LABEL: f2:
184; MIPS32R6:       # %bb.0:
185; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
186; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
187; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
188; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
189; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
190; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
191; MIPS32R6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
192; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
193; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
194; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
195;
196; MMR6-LABEL: f2:
197; MMR6:       # %bb.0:
198; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
199; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
200; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
201; MMR6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
202; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
203; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
204; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
205; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
206; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
207;
208; MIPS4-LABEL: f2:
209; MIPS4:       # %bb.0:
210; MIPS4-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
211; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
212; MIPS4-NEXT:    # <MCOperand Expr:(%highest(b))>>
213; MIPS4-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
214; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
215; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
216; MIPS4-NEXT:    # <MCOperand Expr:(%higher(b))>>
217; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
218; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
219; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
220; MIPS4-NEXT:    # <MCOperand Imm:16>>
221; MIPS4-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
222; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
223; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
224; MIPS4-NEXT:    # <MCOperand Expr:(%hi(b))>>
225; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
226; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
227; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
228; MIPS4-NEXT:    # <MCOperand Imm:16>>
229; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
230; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
231; MIPS4-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
232; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
233; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
234; MIPS4-NEXT:    # <MCOperand Expr:(%lo(b))>>
235;
236; MIPS64R6-LABEL: f2:
237; MIPS64R6:       # %bb.0:
238; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
239; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
240; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
241; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
242; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
243; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
244; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
245; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
246; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
247; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
248; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
249; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
250; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
251; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
252; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
253; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
254; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
255; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
256; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
257; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
258; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
259; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
260; MIPS64R6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
261; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
262; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
263; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
264;
265; MMR5FP64-LABEL: f2:
266; MMR5FP64:       # %bb.0:
267; MMR5FP64-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
268; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
269; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(b))>>
270; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
271; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
272; MMR5FP64-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
273; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
274; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
275; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(b))>>
276;
277; MIPS32R5FP643-LABEL: f2:
278; MIPS32R5FP643:       # %bb.0:
279; MIPS32R5FP643-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
280; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
281; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(b))>>
282; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
283; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
284; MIPS32R5FP643-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
285; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
286; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
287; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(b))>>
288  store i16 %a, ptr @b
289  ret void
290}
291
292define void @f3(i32 %a) {
293; MIPS32-LABEL: f3:
294; MIPS32:       # %bb.0:
295; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
296; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
297; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
298; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
299; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
300; MIPS32-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
301; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
302; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
303; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
304;
305; MMR3-LABEL: f3:
306; MMR3:       # %bb.0:
307; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
308; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
309; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
310; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
311; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
312; MMR3-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
313; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
314; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
315; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
316;
317; MIPS32R6-LABEL: f3:
318; MIPS32R6:       # %bb.0:
319; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
320; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
321; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
322; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
323; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
324; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
325; MIPS32R6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
326; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
327; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
328; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
329;
330; MMR6-LABEL: f3:
331; MMR6:       # %bb.0:
332; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
333; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
334; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
335; MMR6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
336; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
337; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
338; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
339; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
340; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
341;
342; MIPS4-LABEL: f3:
343; MIPS4:       # %bb.0:
344; MIPS4-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
345; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
346; MIPS4-NEXT:    # <MCOperand Expr:(%highest(c))>>
347; MIPS4-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
348; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
349; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
350; MIPS4-NEXT:    # <MCOperand Expr:(%higher(c))>>
351; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
352; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
353; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
354; MIPS4-NEXT:    # <MCOperand Imm:16>>
355; MIPS4-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
356; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
357; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
358; MIPS4-NEXT:    # <MCOperand Expr:(%hi(c))>>
359; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
360; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
361; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
362; MIPS4-NEXT:    # <MCOperand Imm:16>>
363; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
364; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
365; MIPS4-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW64
366; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
367; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
368; MIPS4-NEXT:    # <MCOperand Expr:(%lo(c))>>
369;
370; MIPS64R6-LABEL: f3:
371; MIPS64R6:       # %bb.0:
372; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
373; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
374; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
375; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
376; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
377; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
378; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
379; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
380; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
381; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
382; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
383; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
384; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
385; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
386; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
387; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
388; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
389; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
390; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
391; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
392; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
393; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
394; MIPS64R6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW64
395; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
396; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
397; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
398;
399; MMR5FP64-LABEL: f3:
400; MMR5FP64:       # %bb.0:
401; MMR5FP64-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
402; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
403; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(c))>>
404; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
405; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
406; MMR5FP64-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
407; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
408; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
409; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(c))>>
410;
411; MIPS32R5FP643-LABEL: f3:
412; MIPS32R5FP643:       # %bb.0:
413; MIPS32R5FP643-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
414; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
415; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(c))>>
416; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
417; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
418; MIPS32R5FP643-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
419; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
420; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
421; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(c))>>
422  store i32 %a, ptr @c
423  ret void
424}
425
426define void @f4(i64 %a) {
427; MIPS32-LABEL: f4:
428; MIPS32:       # %bb.0:
429; MIPS32-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
430; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
431; MIPS32-NEXT:    # <MCOperand Expr:(%hi(d))>>
432; MIPS32-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
433; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
434; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
435; MIPS32-NEXT:    # <MCOperand Expr:(%lo(d))>>
436; MIPS32-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
437; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
438; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
439; MIPS32-NEXT:    # <MCOperand Expr:(%lo(d))>>
440; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
441; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
442; MIPS32-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
443; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
444; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
445; MIPS32-NEXT:    # <MCOperand Imm:4>>
446;
447; MMR3-LABEL: f4:
448; MMR3:       # %bb.0:
449; MMR3-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
450; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
451; MMR3-NEXT:    # <MCOperand Expr:(%hi(d))>>
452; MMR3-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
453; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
454; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
455; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
456; MMR3-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
457; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
458; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
459; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
460; MMR3-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
461; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
462; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
463; MMR3-NEXT:    # <MCOperand Imm:4>>
464; MMR3-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
465; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
466;
467; MIPS32R6-LABEL: f4:
468; MIPS32R6:       # %bb.0:
469; MIPS32R6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
470; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
471; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(d))>>
472; MIPS32R6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
473; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
474; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
475; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
476; MIPS32R6-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
477; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
478; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
479; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
480; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
481; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
482; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
483; MIPS32R6-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
484; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
485; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
486; MIPS32R6-NEXT:    # <MCOperand Imm:4>>
487;
488; MMR6-LABEL: f4:
489; MMR6:       # %bb.0:
490; MMR6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
491; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
492; MMR6-NEXT:    # <MCOperand Expr:(%hi(d))>>
493; MMR6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
494; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
495; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
496; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
497; MMR6-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
498; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
499; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
500; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
501; MMR6-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
502; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
503; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
504; MMR6-NEXT:    # <MCOperand Imm:4>>
505; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
506; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
507;
508; MIPS4-LABEL: f4:
509; MIPS4:       # %bb.0:
510; MIPS4-NEXT:    lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
511; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
512; MIPS4-NEXT:    # <MCOperand Expr:(%highest(d))>>
513; MIPS4-NEXT:    daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
514; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
515; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
516; MIPS4-NEXT:    # <MCOperand Expr:(%higher(d))>>
517; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
518; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
519; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
520; MIPS4-NEXT:    # <MCOperand Imm:16>>
521; MIPS4-NEXT:    daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
522; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
523; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
524; MIPS4-NEXT:    # <MCOperand Expr:(%hi(d))>>
525; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
526; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
527; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
528; MIPS4-NEXT:    # <MCOperand Imm:16>>
529; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
530; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
531; MIPS4-NEXT:    sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
532; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
533; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
534; MIPS4-NEXT:    # <MCOperand Expr:(%lo(d))>>
535;
536; MIPS64R6-LABEL: f4:
537; MIPS64R6:       # %bb.0:
538; MIPS64R6-NEXT:    lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
539; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
540; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(d))>>
541; MIPS64R6-NEXT:    daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
542; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
543; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
544; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(d))>>
545; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
546; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
547; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
548; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
549; MIPS64R6-NEXT:    daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
550; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
551; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
552; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(d))>>
553; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
554; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
555; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
556; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
557; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
558; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
559; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
560; MIPS64R6-NEXT:    sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
561; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
562; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
563; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
564;
565; MMR5FP64-LABEL: f4:
566; MMR5FP64:       # %bb.0:
567; MMR5FP64-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
568; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
569; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(d))>>
570; MMR5FP64-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
571; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
572; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
573; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(d))>>
574; MMR5FP64-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
575; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
576; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
577; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(d))>>
578; MMR5FP64-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
579; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
580; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
581; MMR5FP64-NEXT:    # <MCOperand Imm:4>>
582; MMR5FP64-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
583; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
584;
585; MIPS32R5FP643-LABEL: f4:
586; MIPS32R5FP643:       # %bb.0:
587; MIPS32R5FP643-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
588; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
589; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(d))>>
590; MIPS32R5FP643-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
591; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
592; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
593; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(d))>>
594; MIPS32R5FP643-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
595; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
596; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
597; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(d))>>
598; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
599; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
600; MIPS32R5FP643-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
601; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
602; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
603; MIPS32R5FP643-NEXT:    # <MCOperand Imm:4>>
604  store i64 %a, ptr @d
605  ret void
606}
607
608define void @f5(float %e) {
609; MIPS32-LABEL: f5:
610; MIPS32:       # %bb.0:
611; MIPS32-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
612; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
613; MIPS32-NEXT:    # <MCOperand Expr:(%hi(e))>>
614; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
615; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
616; MIPS32-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
617; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
618; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
619; MIPS32-NEXT:    # <MCOperand Expr:(%lo(e))>>
620;
621; MMR3-LABEL: f5:
622; MMR3:       # %bb.0:
623; MMR3-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
624; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
625; MMR3-NEXT:    # <MCOperand Expr:(%hi(e))>>
626; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
627; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
628; MMR3-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
629; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
630; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
631; MMR3-NEXT:    # <MCOperand Expr:(%lo(e))>>
632;
633; MIPS32R6-LABEL: f5:
634; MIPS32R6:       # %bb.0:
635; MIPS32R6-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
636; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
637; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(e))>>
638; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
639; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
640; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
641; MIPS32R6-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
642; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
643; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
644; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(e))>>
645;
646; MMR6-LABEL: f5:
647; MMR6:       # %bb.0:
648; MMR6-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
649; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
650; MMR6-NEXT:    # <MCOperand Expr:(%hi(e))>>
651; MMR6-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
652; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
653; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
654; MMR6-NEXT:    # <MCOperand Expr:(%lo(e))>>
655; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
656; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
657;
658; MIPS4-LABEL: f5:
659; MIPS4:       # %bb.0:
660; MIPS4-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
661; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
662; MIPS4-NEXT:    # <MCOperand Expr:(%highest(e))>>
663; MIPS4-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
664; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
665; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
666; MIPS4-NEXT:    # <MCOperand Expr:(%higher(e))>>
667; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
668; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
669; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
670; MIPS4-NEXT:    # <MCOperand Imm:16>>
671; MIPS4-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
672; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
673; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
674; MIPS4-NEXT:    # <MCOperand Expr:(%hi(e))>>
675; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
676; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
677; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
678; MIPS4-NEXT:    # <MCOperand Imm:16>>
679; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
680; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
681; MIPS4-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
682; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
683; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
684; MIPS4-NEXT:    # <MCOperand Expr:(%lo(e))>>
685;
686; MIPS64R6-LABEL: f5:
687; MIPS64R6:       # %bb.0:
688; MIPS64R6-NEXT:    lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
689; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
690; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(e))>>
691; MIPS64R6-NEXT:    daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
692; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
693; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
694; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(e))>>
695; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
696; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
697; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
698; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
699; MIPS64R6-NEXT:    daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
700; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
701; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
702; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(e))>>
703; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
704; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
705; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
706; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
707; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
708; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
709; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
710; MIPS64R6-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
711; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
712; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
713; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(e))>>
714;
715; MMR5FP64-LABEL: f5:
716; MMR5FP64:       # %bb.0:
717; MMR5FP64-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
718; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
719; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(e))>>
720; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
721; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
722; MMR5FP64-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
723; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
724; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
725; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(e))>>
726;
727; MIPS32R5FP643-LABEL: f5:
728; MIPS32R5FP643:       # %bb.0:
729; MIPS32R5FP643-NEXT:    lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
730; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
731; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(e))>>
732; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
733; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
734; MIPS32R5FP643-NEXT:    swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
735; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
736; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
737; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(e))>>
738  store float %e, ptr @e
739  ret void
740}
741
742define void @f6(double %f) {
743; MIPS32-LABEL: f6:
744; MIPS32:       # %bb.0:
745; MIPS32-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
746; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
747; MIPS32-NEXT:    # <MCOperand Expr:(%hi(f))>>
748; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
749; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
750; MIPS32-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1
751; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
752; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
753; MIPS32-NEXT:    # <MCOperand Expr:(%lo(f))>>
754;
755; MMR3-LABEL: f6:
756; MMR3:       # %bb.0:
757; MMR3-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
758; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
759; MMR3-NEXT:    # <MCOperand Expr:(%hi(f))>>
760; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
761; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
762; MMR3-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_MM_D32
763; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
764; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
765; MMR3-NEXT:    # <MCOperand Expr:(%lo(f))>>
766;
767; MIPS32R6-LABEL: f6:
768; MIPS32R6:       # %bb.0:
769; MIPS32R6-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
770; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
771; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(f))>>
772; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
773; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
774; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
775; MIPS32R6-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
776; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
777; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
778; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(f))>>
779;
780; MMR6-LABEL: f6:
781; MMR6:       # %bb.0:
782; MMR6-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
783; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
784; MMR6-NEXT:    # <MCOperand Expr:(%hi(f))>>
785; MMR6-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_D64_MMR6
786; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
787; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
788; MMR6-NEXT:    # <MCOperand Expr:(%lo(f))>>
789; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
790; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
791;
792; MIPS4-LABEL: f6:
793; MIPS4:       # %bb.0:
794; MIPS4-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
795; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
796; MIPS4-NEXT:    # <MCOperand Expr:(%highest(f))>>
797; MIPS4-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
798; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
799; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
800; MIPS4-NEXT:    # <MCOperand Expr:(%higher(f))>>
801; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
802; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
803; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
804; MIPS4-NEXT:    # <MCOperand Imm:16>>
805; MIPS4-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
806; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
807; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
808; MIPS4-NEXT:    # <MCOperand Expr:(%hi(f))>>
809; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
810; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
811; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
812; MIPS4-NEXT:    # <MCOperand Imm:16>>
813; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
814; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
815; MIPS4-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
816; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
817; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
818; MIPS4-NEXT:    # <MCOperand Expr:(%lo(f))>>
819;
820; MIPS64R6-LABEL: f6:
821; MIPS64R6:       # %bb.0:
822; MIPS64R6-NEXT:    lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
823; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
824; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(f))>>
825; MIPS64R6-NEXT:    daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
826; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
827; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
828; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(f))>>
829; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
830; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
831; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
832; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
833; MIPS64R6-NEXT:    daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
834; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
835; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
836; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(f))>>
837; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
838; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
839; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
840; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
841; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
842; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
843; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
844; MIPS64R6-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
845; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
846; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
847; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(f))>>
848;
849; MMR5FP64-LABEL: f6:
850; MMR5FP64:       # %bb.0:
851; MMR5FP64-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
852; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
853; MMR5FP64-NEXT:    # <MCOperand Expr:(%hi(f))>>
854; MMR5FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
855; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
856; MMR5FP64-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_MM_D64
857; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
858; MMR5FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
859; MMR5FP64-NEXT:    # <MCOperand Expr:(%lo(f))>>
860;
861; MIPS32R5FP643-LABEL: f6:
862; MIPS32R5FP643:       # %bb.0:
863; MIPS32R5FP643-NEXT:    lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
864; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
865; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%hi(f))>>
866; MIPS32R5FP643-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
867; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
868; MIPS32R5FP643-NEXT:    sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
869; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
870; MIPS32R5FP643-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
871; MIPS32R5FP643-NEXT:    # <MCOperand Expr:(%lo(f))>>
872  store double %f, ptr @f
873  ret void
874}
875