| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 133 const TargetRegisterClass *TRC) { in usesRegClass() argument
269 const TargetRegisterClass *TRC = optimizeSDPattern() local
432 createExtractSubreg(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,const DebugLoc & DL,unsigned DReg,unsigned Lane,const TargetRegisterClass * TRC) createExtractSubreg() argument
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| H A D | ARMLoadStoreOptimizer.cpp | 2430 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps() local
3025 const TargetRegisterClass *TRC = TII->getRegClass(MCID, BaseOp, TRI, *MF); AdjustBaseAndOffset() local
3082 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); createPostIncLoadStore() local
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| H A D | ARMBaseInstrInfo.cpp | 3433 const TargetRegisterClass *TRC = MRI->getRegClass(Reg); foldImmediate() local
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyAsmPrinter.cpp | 64 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); getRegType() local
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| H A D | WebAssemblyISelLowering.cpp | 571 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); LowerCallResults() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 526 const TargetRegisterClass *TRC = EmitSubregNode() local
682 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); EmitRegSequence() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86AvoidStoreForwardingBlocks.cpp | 557 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, getRegSizeInBytes() local
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 511 return TRC.getLaneMask(); in getMaxLaneMaskForVReg() local
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| H A D | LiveDebugVariables.cpp | 1542 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); rewriteLocations() local
1854 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); emitDebugValues() local
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| H A D | RegAllocPBQP.cpp | 617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); initializeGraph() local
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| H A D | MachinePipeliner.cpp | 1328 for (const TargetRegisterClass *TRC : TRI->regclasses()) { computePressureSetLimit() local
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| /llvm-project/clang/include/clang/AST/ |
| H A D | ASTNodeTraverser.h | 529 if (const Expr *TRC = D->getTrailingRequiresClause()) VisitFunctionDecl() local
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| H A D | Decl.h | 2664 if (auto *TRC = getTrailingRequiresClause()) getAssociatedConstraints() local
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| /llvm-project/clang/lib/Sema/ |
| H A D | SemaTemplateVariadic.cpp | 989 if (Expr *TRC = D.getTrailingRequiresClause()) containsUnexpandedParameterPacks() local
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| H A D | SemaLambda.cpp | 1514 if (Expr *TRC = Method->getTrailingRequiresClause()) { ActOnStartOfLambdaDefinition() local
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| H A D | SemaLookup.cpp | 5361 CorrectTypoDelayed(const DeclarationNameInfo & TypoName,Sema::LookupNameKind LookupKind,Scope * S,CXXScopeSpec * SS,CorrectionCandidateCallback & CCC,TypoDiagnosticGenerator TDG,TypoRecoveryCallback TRC,CorrectTypoKind Mode,DeclContext * MemberContext,bool EnteringContext,const ObjCObjectPointerType * OPT) CorrectTypoDelayed() argument
5718 createDelayedTypo(std::unique_ptr<TypoCorrectionConsumer> TCC,TypoDiagnosticGenerator TDG,TypoRecoveryCallback TRC,SourceLocation TypoLoc) createDelayedTypo() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1169 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 simplifyCode() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 1404 isOfRegClass(const TargetInstrInfo::RegSubRegPair & P,const TargetRegisterClass & TRC,MachineRegisterInfo & MRI) isOfRegClass() argument
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| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 83 DstOp(const TargetRegisterClass * TRC) DstOp() argument
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4144 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); isHForm() local
4158 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); isQForm() local
4203 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); isFpOrNEON() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1842 const TargetRegisterClass *TRC = SelectInlineAsmMemoryOperand() local
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| /llvm-project/clang/lib/AST/ |
| H A D | DeclTemplate.cpp | 274 if (const Expr *TRC = FD->getTrailingRequiresClause()) getAssociatedConstraints() local
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| /llvm-project/clang/include/clang/Sema/ |
| H A D | DeclSpec.h | 2626 setTrailingRequiresClause(Expr * TRC) setTrailingRequiresClause() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2103 const TargetRegisterClass *TRC; createVR() local
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| /llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.cpp | 1530 const TargetRegisterClass *TRC = nullptr; getValueForInstrRef() local
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