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Searched defs:Stage (Results 1 – 20 of 20) sorted by relevance

/llvm-project/llvm/lib/ObjectYAML/
H A DDXContainerYAML.cpp53 uint16_t Stage) in PSVInfo() argument
154 Triple::EnvironmentType Stage = dxbc::getShaderStage(PSV.Info.ShaderStage); in mapping() local
279 Triple::EnvironmentType Stage = dxbc::getShaderStage(Info.ShaderStage); mapInfoForVersion() local
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/llvm-project/llvm/lib/DWARFLinker/Parallel/
H A DDWARFLinkerCompileUnit.h56 enum class Stage : uint8_t { enum
101 void setStage(Stage Stage) { this->Stage = Stage; } in setStage() argument
717 std::atomic<Stage> Stage; variable
/llvm-project/llvm/lib/CodeGen/
H A DRegAllocGreedy.h68 LiveRangeStage Stage = RS_New; global() member
90 setStage(Register Reg,LiveRangeStage Stage) setStage() argument
95 setStage(const LiveInterval & VirtReg,LiveRangeStage Stage) setStage() argument
H A DMLRegAllocPriorityAdvisor.cpp298 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); getPriorityImpl() local
H A DModuloSchedule.cpp1616 int Stage = getStage(MI); filterInstructions() local
1641 moveStageBetweenBlocks(MachineBasicBlock * DestBB,MachineBasicBlock * SourceBB,unsigned Stage) moveStageBetweenBlocks() argument
1796 unsigned Stage = Schedule.getNumStages() - 1 + I - J; peelPrologAndEpilogs() local
1929 int Stage = getStage(MI); rewriteUsesOf() local
2793 parseSymbolString(StringRef S,int & Cycle,int & Stage) parseSymbolString() argument
2817 DenseMap<MachineInstr *, int> Cycle, Stage; runOnLoop() local
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H A DRegAllocGreedy.cpp292 auto Stage = ExtraInfo->getOrInitStage(Reg); enqueue() local
309 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); getPriority() local
2439 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg); selectOrSplitImpl() local
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H A DMachinePipeliner.cpp1082 for (int Stage = 0, LastStage = Schedule.getMaxStageCount(); computeScheduledInsts() local
1486 const auto Stage = Stages[MI]; computeMaxSetPressure() local
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/llvm-project/llvm/lib/MC/
H A DDXContainerPSVInfo.cpp150 void PSVRuntimeInfo::finalize(Triple::EnvironmentType Stage) { in finalize()
/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h94 DenseMap<MachineInstr *, int> Stage; variable
110 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule() argument
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/llvm-project/llvm/utils/TableGen/
H A DDFAPacketizerEmitter.cpp277 for (NfaStateTy Stage : InsnClass) { emitForItineraries() local
H A DSubtargetEmitter.cpp364 const Record *Stage = StageList[i]; FormItineraryStageString() local
/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp442 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources() local
471 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp734 auto Stage = createSchedStage(S.getCurrentStage()); runSchedStages() local
/llvm-project/clang/lib/Sema/
H A DSemaHLSL.cpp287 DiagnoseAttrStageMismatch(const Attr * A,llvm::Triple::EnvironmentType Stage,std::initializer_list<llvm::Triple::EnvironmentType> AllowedStages) DiagnoseAttrStageMismatch() argument
/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h612 enum InstrStage Stage; variable
/llvm-project/llvm/include/llvm/BinaryFormat/
H A DDXContainer.h247 void swapBytes(Triple::EnvironmentType Stage) { in swapBytes() argument
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/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2820 for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) { SelectMVE_VLD() local
H A DARMBaseInstrInfo.cpp6886 for (int Stage = 0, StageEnd = SMS.getMaxStageCount(); Stage <= StageEnd; tooMuchRegisterPressure() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp17735 for (unsigned Stage = 0; Stage != 6; ++Stage) { computeGREVOrGORC() local
/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp5181 for (unsigned Stage = 0; Stage != Repetitions; ++Stage) { createPackShuffleMask() local
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