/llvm-project/llvm/lib/ObjectYAML/ |
H A D | DXContainerYAML.cpp | 53 uint16_t Stage) in PSVInfo() argument 154 Triple::EnvironmentType Stage = dxbc::getShaderStage(PSV.Info.ShaderStage); in mapping() local 279 Triple::EnvironmentType Stage = dxbc::getShaderStage(Info.ShaderStage); mapInfoForVersion() local [all...] |
/llvm-project/llvm/lib/DWARFLinker/Parallel/ |
H A D | DWARFLinkerCompileUnit.h | 56 enum class Stage : uint8_t { enum 101 void setStage(Stage Stage) { this->Stage = Stage; } in setStage() argument 717 std::atomic<Stage> Stage; variable
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/llvm-project/llvm/lib/CodeGen/ |
H A D | RegAllocGreedy.h | 68 LiveRangeStage Stage = RS_New; global() member 90 setStage(Register Reg,LiveRangeStage Stage) setStage() argument 95 setStage(const LiveInterval & VirtReg,LiveRangeStage Stage) setStage() argument
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H A D | MLRegAllocPriorityAdvisor.cpp | 298 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); getPriorityImpl() local
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H A D | ModuloSchedule.cpp | 1616 int Stage = getStage(MI); filterInstructions() local 1641 moveStageBetweenBlocks(MachineBasicBlock * DestBB,MachineBasicBlock * SourceBB,unsigned Stage) moveStageBetweenBlocks() argument 1796 unsigned Stage = Schedule.getNumStages() - 1 + I - J; peelPrologAndEpilogs() local 1929 int Stage = getStage(MI); rewriteUsesOf() local 2793 parseSymbolString(StringRef S,int & Cycle,int & Stage) parseSymbolString() argument 2817 DenseMap<MachineInstr *, int> Cycle, Stage; runOnLoop() local [all...] |
H A D | RegAllocGreedy.cpp | 292 auto Stage = ExtraInfo->getOrInitStage(Reg); enqueue() local 309 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); getPriority() local 2439 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg); selectOrSplitImpl() local [all...] |
H A D | MachinePipeliner.cpp | 1082 for (int Stage = 0, LastStage = Schedule.getMaxStageCount(); computeScheduledInsts() local 1486 const auto Stage = Stages[MI]; computeMaxSetPressure() local [all...] |
/llvm-project/llvm/lib/MC/ |
H A D | DXContainerPSVInfo.cpp | 150 void PSVRuntimeInfo::finalize(Triple::EnvironmentType Stage) { in finalize()
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/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ModuloSchedule.h | 94 DenseMap<MachineInstr *, int> Stage; variable 110 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule() argument [all...] |
/llvm-project/llvm/utils/TableGen/ |
H A D | DFAPacketizerEmitter.cpp | 277 for (NfaStateTy Stage : InsnClass) { emitForItineraries() local
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H A D | SubtargetEmitter.cpp | 364 const Record *Stage = StageList[i]; FormItineraryStageString() local
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/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.cpp | 442 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources() local 471 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | GCNSchedStrategy.cpp | 734 auto Stage = createSchedStage(S.getCurrentStage()); runSchedStages() local
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/llvm-project/clang/lib/Sema/ |
H A D | SemaHLSL.cpp | 287 DiagnoseAttrStageMismatch(const Attr * A,llvm::Triple::EnvironmentType Stage,std::initializer_list<llvm::Triple::EnvironmentType> AllowedStages) DiagnoseAttrStageMismatch() argument
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/llvm-project/llvm/include/llvm/MCA/ |
H A D | Instruction.h | 612 enum InstrStage Stage; variable
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/llvm-project/llvm/include/llvm/BinaryFormat/ |
H A D | DXContainer.h | 247 void swapBytes(Triple::EnvironmentType Stage) { in swapBytes() argument [all...] |
/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 2820 for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) { SelectMVE_VLD() local
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H A D | ARMBaseInstrInfo.cpp | 6886 for (int Stage = 0, StageEnd = SMS.getMaxStageCount(); Stage <= StageEnd; tooMuchRegisterPressure() local
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/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 17735 for (unsigned Stage = 0; Stage != 6; ++Stage) { computeGREVOrGORC() local
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 5181 for (unsigned Stage = 0; Stage != Repetitions; ++Stage) { createPackShuffleMask() local [all...] |