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Searched defs:SrcReg (Results 1 – 25 of 161) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp136 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
156 Register SrcReg = Src2.getReg(); in runOnMachineFunction() local
173 Register SrcReg = Src1.getReg(); in runOnMachineFunction() local
184 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
206 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h67 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); tryCombineAnyExt() local
121 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); tryCombineZExt() local
195 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); tryCombineSExt() local
254 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); tryCombineTrunc() local
547 replaceRegOrBuildCopy(Register DstReg,Register SrcReg,MachineRegisterInfo & MRI,MachineIRBuilder & Builder,SmallVectorImpl<Register> & UpdatedDefs,GISelChangeObserver & Observer) replaceRegOrBuildCopy() argument
618 Register SrcReg = Concat.getReg(StartSrcIdx); findValueFromConcat() local
766 Register SrcReg = MI.getOperand(1).getReg(); findValueFromExt() local
792 Register SrcReg = MI.getOperand(1).getReg(); findValueFromTrunc() local
825 Register SrcReg = Def->getOperand(Def->getNumOperands() - 1).getReg(); findValueFromDefImpl() local
1042 Register SrcReg = MI.getSourceReg(); tryCombineUnmergeValues() local
1224 Register SrcReg = MergeI->getOperand(Idx + 1).getReg(); tryCombineUnmergeValues() local
1251 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); tryCombineExtract() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp215 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg, in emitInstStore() argument
806 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Addres argument
907 unsigned SrcReg = 0; selectStore() local
997 Register SrcReg = selectFPExt() local
1076 Register SrcReg = getRegForValue(Src); selectFPTrunc() local
1112 Register SrcReg = getRegForValue(Src); selectFPToInt() local
1458 unsigned SrcReg = Allocation[ArgNo].Reg; fastLowerArguments() local
1591 Register SrcReg = getRegForValue(II->getOperand(0)); fastLowerIntrinsicCall() local
1721 unsigned SrcReg = Reg + VA.getValNo(); selectRet() local
1785 Register SrcReg = getRegForValue(Op); selectTrunc() local
1801 Register SrcReg = getRegForValue(Src); selectIntExt() local
1823 emitIntSExt32r1(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg) emitIntSExt32r1() argument
1842 emitIntSExt32r2(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg) emitIntSExt32r2() argument
1857 emitIntSExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg) emitIntSExt() argument
1866 emitIntZExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg) emitIntZExt() argument
1888 emitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg,bool IsZExt) emitIntExt() argument
1902 emitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,bool isZExt) emitIntExt() argument
[all...]
H A DMipsSEInstrInfo.cpp86 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
216 storeRegToStack(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,int64_t Offset) const storeRegToStack() argument
733 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; expandCvtFPInt() local
756 Register SrcReg = I->getOperand(1).getReg(); expandExtractElementF64() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp211 __anon60fd32f40302(MachineInstr &MI, OpcodePair Opcode, unsigned Imm0, unsigned Imm1, Register SrcReg, Register NewTmpReg, Register NewDstReg) visitAND() argument
275 Register SrcReg = MI.getOperand(2).getReg(); visitORR() local
384 __anon60fd32f40502(MachineInstr &MI, OpcodePair Opcode, unsigned Imm0, unsigned Imm1, Register SrcReg, Register NewTmpReg, Register NewDstReg) visitADDSUB() argument
430 __anon60fd32f40702(MachineInstr &MI, OpcodePair Opcode, unsigned Imm0, unsigned Imm1, Register SrcReg, Register NewTmpReg, Register NewDstReg) visitADDSSUBS() argument
533 Register SrcReg = MI.getOperand(1).getReg(); splitTwoPartImm() local
597 Register SrcReg = SrcMI->getOperand(1).getReg(); visitINSviGPR() local
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H A DAArch64RedundantCopyElimination.cpp186 MCPhysReg SrcReg = PredI.getOperand(1).getReg(); in knownRegValInBlock() local
382 Register SrcReg = IsCopy ? MI->getOperand(1).getReg() : Register(); in optimizeBlock() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp121 Register SrcReg = MI.getOperand(1).getReg(); getInstrMapping() local
156 Register SrcReg = MI.getOperand(1).getReg(); getInstrMapping() local
166 Register SrcReg = MI.getOperand(0).getReg(); getInstrMapping() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp34 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg()
47 Register SrcReg = MI->getOperand(1).getReg(); in expandMEMCPY() local
126 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot()
H A DBPFMISimplifyPatchable.cpp190 processCandidate(MachineRegisterInfo * MRI,MachineBasicBlock & MBB,MachineInstr & MI,Register & SrcReg,Register & DstReg,const GlobalValue * GVal,bool IsAma) processCandidate() argument
225 processDstReg(MachineRegisterInfo * MRI,Register & DstReg,Register & SrcReg,const GlobalValue * GVal,bool doSrcRegProp,bool IsAma) processDstReg() argument
330 Register SrcReg = MI.getOperand(1).getReg(); removeLD() local
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp229 Register SrcReg = Src.getReg(); computeKnownBitsImpl() local
457 Register SrcReg = MI.getOperand(1).getReg(); computeKnownBitsImpl() local
503 Register SrcReg = MI.getOperand(NumOps - 1).getReg(); computeKnownBitsImpl() local
520 Register SrcReg = MI.getOperand(1).getReg(); computeKnownBitsImpl() local
526 Register SrcReg = MI.getOperand(1).getReg(); computeKnownBitsImpl() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp150 unsigned SrcReg, unsigned Flag = 0, in copyRegToRegClass() argument
618 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { in PPCEmitStore() argument
735 unsigned SrcReg = 0; SelectStore() local
963 Register SrcReg = getRegForValue(Src); SelectFPExt() local
981 Register SrcReg = getRegForValue(Src); SelectFPTrunc() local
1017 PPCMoveToFPReg(MVT SrcVT,unsigned SrcReg,bool IsSigned) PPCMoveToFPReg() argument
1082 Register SrcReg = getRegForValue(Src); SelectIToFP() local
1153 PPCMoveToIntReg(const Instruction * I,MVT VT,unsigned SrcReg,bool IsSigned) PPCMoveToIntReg() argument
1209 Register SrcReg = getRegForValue(Src); SelectFPToI() local
1728 unsigned SrcReg = SelectRet() local
1748 unsigned SrcReg = Reg + VA.getValNo(); SelectRet() local
1807 PPCEmitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg,bool IsZExt) PPCEmitIntExt() argument
1887 Register SrcReg = getRegForValue(Src); SelectTrunc() local
1906 Register SrcReg = getRegForValue(Src); SelectIntExt() local
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H A DPPCRegisterInfo.h26 inline static unsigned getCRFromCRBit(unsigned SrcReg) { in getCRFromCRBit()
H A DPPCRegisterInfo.cpp970 Register SrcReg = MI.getOperand(0).getReg(); in lowerCRSpilling() local
1059 Register SrcReg = MI.getOperand(0).getReg(); in lowerCRBitSpilling() local
1212 emitAccCopyInfo(MachineBasicBlock & MBB,MCRegister DestReg,MCRegister SrcReg) emitAccCopyInfo() argument
1240 spillRegPairs(MachineBasicBlock & MBB,MachineBasicBlock::iterator II,DebugLoc DL,const TargetInstrInfo & TII,Register SrcReg,unsigned FrameIndex,bool IsLittleEndian,bool IsKilled,bool TwoPairs) spillRegPairs() argument
1287 Register SrcReg = MI.getOperand(0).getReg(); lowerOctWordSpilling() local
1321 Register SrcReg = MI.getOperand(0).getReg(); lowerACCSpilling() local
1406 Register SrcReg = MI.getOperand(0).getReg(); lowerWACCSpilling() local
1466 Register SrcReg = MI.getOperand(0).getReg(); lowerQuadwordSpilling() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp42 copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const copyPhysReg() argument
80 storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const storeRegToStackSlot() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DPHIEliminationUtils.cpp22 unsigned SrcReg) { in findPHICopyInsertPoint()
H A DTwoAddressInstructionPass.cpp289 isCopyToReg(MachineInstr & MI,Register & SrcReg,Register & DstReg,bool & IsSrcPhys,bool & IsDstPhys) const isCopyToReg() argument
387 Register SrcReg, DstReg; isKilled() local
429 Register SrcReg; findOnlyInterestingUse() local
501 for (auto SrcReg : Srcs) removeMapRegEntry() local
813 Register SrcReg, DstReg; processCopy() local
1450 Register SrcReg = SrcMO.getReg(); collectTiedOperands() local
1831 Register SrcReg = mi->getOperand(SrcIdx).getReg(); runOnMachineFunction() local
1942 Register SrcReg = UseMO.getReg(); eliminateRegSequence() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp276 Register SrcReg = I.getOperand(1).getReg(); selectCopy() local
742 selectTurnIntoCOPY(MachineInstr & I,MachineRegisterInfo & MRI,const unsigned DstReg,const TargetRegisterClass * DstRC,const unsigned SrcReg,const TargetRegisterClass * SrcRC) const selectTurnIntoCOPY() argument
763 const Register SrcReg = I.getOperand(1).getReg(); selectTruncOrPtrToInt() local
827 const Register SrcReg = I.getOperand(1).getReg(); selectZext() local
892 const Register SrcReg = I.getOperand(1).getReg(); selectAnyext() local
1196 const Register SrcReg = I.getOperand(1).getReg(); selectExtract() local
1246 emitExtractSubreg(unsigned DstReg,unsigned SrcReg,MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const emitExtractSubreg() argument
1284 emitInsertSubreg(unsigned DstReg,unsigned SrcReg,MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const emitInsertSubreg() argument
1328 const Register SrcReg = I.getOperand(1).getReg(); selectInsert() local
1387 Register SrcReg = I.getOperand(NumDefs).getReg(); selectUnmergeValues() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp212 unsigned SrcReg = getCompareSourceReg(Compare); in convertToBRCT() local
256 unsigned SrcReg = getCompareSourceReg(Compare); in convertToLoadAndTrap() local
511 unsigned SrcReg = getCompareSourceReg(Compare); optimizeCompareZero() local
614 Register SrcReg = Compare.getOperand(0).getReg(); fuseCompareOperations() local
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H A DSystemZPostRewrite.cpp83 Register SrcReg = MBBI->getOperand(2).getReg(); in selectLOCRMux() local
158 Register SrcReg = MI.getOperand(2).getReg(); in expandCondMove() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp155 Register SrcReg = MI.getOperand(2).getReg(); in expandArith() local
188 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic() local
498 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
531 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
662 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
707 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
740 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
772 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
840 Register SrcReg = MI.getOperand(1).getReg(); in expandLPMWELPMW() local
952 Register SrcReg = MI.getOperand(1).getReg(); in expandLPMBELPMB() local
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp384 isSignExtendedW(Register SrcReg,const RISCVSubtarget & ST,const MachineRegisterInfo & MRI,SmallPtrSetImpl<MachineInstr * > & FixableDef) isSignExtendedW() argument
391 __anon6edae8620202(Register SrcReg) isSignExtendedW() argument
635 Register SrcReg = MI.getOperand(1).getReg(); removeSExtWInstrs() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
536 unsigned DstReg, SrcReg; in subInstWouldBeExtended() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp37 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, in storeRegToStackSlot()
93 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp42 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
111 storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register SrcReg,bool IsKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const storeRegToStackSlot() argument
187 Register SrcReg = LoongArch::R0; movImm() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCombinerHelper.cpp404 Register SrcReg = Def->getOperand(1).getReg(); in isFPExtFromF16OrConst() local
423 Register SrcReg = MI.getOperand(1).getReg(); in matchExpandPromotedF16FMed3() local

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