Lines Matching defs:SrcReg

42                                      MCRegister SrcReg, bool KillSrc) const {
43   if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
45         .addReg(SrcReg, getKillRegState(KillSrc))
51   if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) {
53         .addReg(SrcReg, getKillRegState(KillSrc))
59   if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) {
61         .addReg(SrcReg, getKillRegState(KillSrc))
68       LoongArch::GPRRegClass.contains(SrcReg)) {
70         .addReg(SrcReg, getKillRegState(KillSrc));
75       LoongArch::CFRRegClass.contains(SrcReg)) {
77         .addReg(SrcReg, getKillRegState(KillSrc));
81   if (LoongArch::CFRRegClass.contains(DstReg, SrcReg)) {
83         .addReg(SrcReg, getKillRegState(KillSrc));
89   if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
91   } else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
94              LoongArch::FPR32RegClass.contains(SrcReg)) {
98              LoongArch::FPR64RegClass.contains(SrcReg)) {
107       .addReg(SrcReg, getKillRegState(KillSrc));
111     MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
140       .addReg(SrcReg, getKillRegState(IsKill))
187   Register SrcReg = LoongArch::R0;
207           .addReg(SrcReg, RegState::Kill)
216     SrcReg = DstReg;