Lines Matching defs:SrcReg

86                                   MCRegister SrcReg, bool KillSrc) const {
91     if (Mips::GPR32RegClass.contains(SrcReg)) {
96     } else if (Mips::CCRRegClass.contains(SrcReg))
98     else if (Mips::FGR32RegClass.contains(SrcReg))
100     else if (Mips::HI32RegClass.contains(SrcReg)) {
102       SrcReg = 0;
103     } else if (Mips::LO32RegClass.contains(SrcReg)) {
105       SrcReg = 0;
106     } else if (Mips::HI32DSPRegClass.contains(SrcReg))
108     else if (Mips::LO32DSPRegClass.contains(SrcReg))
110     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
112         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
115     else if (Mips::MSACtrlRegClass.contains(SrcReg))
118   else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
133         .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
139           .addReg(SrcReg, getKillRegState(KillSrc));
143   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
145   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
147   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
150     if (Mips::GPR64RegClass.contains(SrcReg))
152     else if (Mips::HI64RegClass.contains(SrcReg))
153       Opc = Mips::MFHI64, SrcReg = 0;
154     else if (Mips::LO64RegClass.contains(SrcReg))
155       Opc = Mips::MFLO64, SrcReg = 0;
156     else if (Mips::FGR64RegClass.contains(SrcReg))
159   else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
168     if (Mips::MSA128BRegClass.contains(SrcReg))
179   if (SrcReg)
180     MIB.addReg(SrcReg, getKillRegState(KillSrc));
216                 Register SrcReg, bool isKill, int FI,
270       SrcReg = Mips::K0;
273       SrcReg = Mips::K0_64;
276       SrcReg = Mips::K0;
279       SrcReg = Mips::K0_64;
284   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
733   unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
747   BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
756   Register SrcReg = I->getOperand(1).getReg();
762   Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
789         .addReg(SrcReg);