Lines Matching defs:SrcReg

113                           const unsigned SrcReg,
124   bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
127   bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
283   Register SrcReg = I.getOperand(1).getReg();
284   const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
285   const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
294           getRegClass(MRI.getType(SrcReg), SrcRegBank);
304             .addReg(SrcReg)
314   assert((!SrcReg.isPhysical() || I.isCopy()) &&
319           (SrcReg.isPhysical() &&
320            DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
328       SrcReg.isPhysical()) {
331     const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg);
335       I.getOperand(1).substPhysReg(SrcReg, TRI);
339   // No need to constrain SrcReg. It will get constrained when
776     const TargetRegisterClass *DstRC, const unsigned SrcReg,
779   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
797   const Register SrcReg = I.getOperand(1).getReg();
800   const LLT SrcTy = MRI.getType(SrcReg);
803   const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
821     return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
842   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
861   const Register SrcReg = I.getOperand(1).getReg();
864   const LLT SrcTy = MRI.getType(SrcReg);
894   Register DefReg = SrcReg;
905         .addReg(SrcReg)
926   const Register SrcReg = I.getOperand(1).getReg();
929   const LLT SrcTy = MRI.getType(SrcReg);
932   const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
947     return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
952   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
968       .addReg(SrcReg)
1230   const Register SrcReg = I.getOperand(1).getReg();
1234   const LLT SrcTy = MRI.getType(SrcReg);
1245     if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF))
1280 bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg,
1285   const LLT SrcTy = MRI.getType(SrcReg);
1302   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1306   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1313       .addReg(SrcReg, 0, SubIdx);
1318 bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg,
1323   const LLT SrcTy = MRI.getType(SrcReg);
1340   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1343   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1351       .addReg(SrcReg);
1362   const Register SrcReg = I.getOperand(1).getReg();
1376   if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) {
1421   Register SrcReg = I.getOperand(NumDefs).getReg();
1428              .addReg(SrcReg)