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Searched defs:Src2 (Results 1 – 25 of 40) sorted by relevance

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/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp109 GenericValue Src2, Type *Ty) { in executeFAddInst()
120 GenericValue Src2, Type *Ty) { in executeFSubInst()
131 GenericValue Src2, Type *Ty) { in executeFMulInst()
142 GenericValue Src2, Type *Ty) { in executeFDivInst()
153 GenericValue Src2, Type *Ty) { in executeFRemInst()
192 static GenericValue executeICMP_EQ(GenericValue Src1, GenericValue Src2, in executeICMP_EQ()
206 static GenericValue executeICMP_NE(GenericValue Src1, GenericValue Src2, in executeICMP_NE()
220 static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue Src2, in executeICMP_ULT()
234 static GenericValue executeICMP_SLT(GenericValue Src1, GenericValue Src2, in executeICMP_SLT()
248 static GenericValue executeICMP_UGT(GenericValue Src1, GenericValue Src2, in executeICMP_UGT()
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMacroFusion.cpp46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent() local
H A DAMDGPUCombinerHelper.cpp421 matchExpandPromotedF16FMed3(MachineInstr & MI,Register Src0,Register Src1,Register Src2) matchExpandPromotedF16FMed3() argument
434 applyExpandPromotedF16FMed3(MachineInstr & MI,Register Src0,Register Src1,Register Src2) applyExpandPromotedF16FMed3() argument
H A DSIShrinkInstructions.cpp420 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); shrinkMadFma() local
977 const MachineOperand *Src2 = runOnMachineFunction() local
1005 const MachineOperand *Src2 = TII->getNamedOperand(MI, runOnMachineFunction() local
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H A DGCNDPPCombine.cpp344 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); createDPPInst() local
691 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); combineDPPMov() local
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H A DSIOptimizeExecMasking.cpp146 const MachineOperand &Src2 = MI.getOperand(2); isLogicalOpOnExec() local
162 const MachineOperand &Src2 = MI.getOperand(2); isLogicalOpOnExec() local
H A DSIPeepholeSDWA.cpp668 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); matchSDWAOperand() local
1087 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); convertToSDWA() local
H A DAMDGPURegBankCombiner.cpp318 MachineInstr *Src2 = getDefIgnoringCopies(MI.getOperand(3).getReg(), MRI); matchFPMed3ToClamp() local
H A DAMDGPUInstCombineIntrinsic.cpp46 const APFloat &Src2) { in fmed3AMDGCN() argument
765 Value *Src2 = II.getArgOperand(2); instCombineIntrinsic() local
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H A DSIInstrInfo.cpp3525 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2); foldImmediate() local
3936 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); convertToThreeAddress() local
4415 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); canShrink() local
4501 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); buildShrunkInst() local
5006 const MachineOperand &Src2 = MI.getOperand(Src2Idx); verifyInstruction() local
5975 MachineOperand &Src2 = MI.getOperand(VOP3Idx[2]); legalizeOperandsVOP3() local
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H A DSIISelLowering.cpp5121 MachineOperand &Src2 = MI.getOperand(4); EmitInstrWithCustomInserter() local
6124 __anon7a836d960102(SDValue Src0, SDValue Src1, SDValue Src2, MVT ValT) lowerLaneOp() argument
6161 SDValue Src1, Src2; lowerLaneOp() local
13273 SDValue Src2 = N->getOperand(2); performFMed3Combine() local
14183 SDValue Src2 = performAddCombine() local
15062 SDValue Src2 = Node->getOperand(5); PostISelFolding() local
15257 if (auto *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2)) { AdjustInstrPostInstrSelection() local
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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp152 Register SrcReg = Src2.getReg(); in runOnMachineFunction() local
169 MachineOperand &Src2 = MI.getOperand(2); runOnMachineFunction() local
H A DHexagonGenMux.cpp299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); genMuxInBlock() local
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H A DHexagonConstPropagation.cpp2576 const MachineOperand &Src2 = MI.getOperand(2); evaluateHexCompare() local
2598 evaluateHexCompare2(unsigned Opc,const MachineOperand & Src1,const MachineOperand & Src2,const CellMap & Inputs,bool & Result) evaluateHexCompare2() argument
2633 const MachineOperand &Src2 = MI.getOperand(2); evaluateHexLogical() local
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/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp174 EmitTargetCodeForMemcmp(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src1,SDValue Src2,SDValue Size,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) const EmitTargetCodeForMemcmp() argument
226 EmitTargetCodeForStrcmp(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src1,SDValue Src2,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) const EmitTargetCodeForStrcmp() argument
H A DSystemZISelLowering.cpp4602 SDValue Src2 = Node->getVal(); lowerATOMIC_LOAD_OP() local
4657 SDValue Src2 = Node->getVal(); lowerATOMIC_LOAD_SUB() local
8568 MachineOperand Src2 = earlyUseOperand(MI.getOperand(3)); emitAtomicLoadBinary() local
8663 Register Src2 = MI.getOperand(3).getReg(); emitAtomicLoadMinMax() local
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/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp136 EmitBinary(MCStreamer & OutStreamer,unsigned Opcode,MCOperand & RS1,MCOperand & Src2,MCOperand & RD,const MCSubtargetInfo & STI) EmitBinary() argument
/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp154 emitBinary(MCStreamer & OutStreamer,unsigned Opcode,MCOperand & RS1,MCOperand & Src2,MCOperand & RD,const MCSubtargetInfo & STI) emitBinary() argument
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp751 Register Src2 = MI.getOperand(2).getReg(); computeNumSignBits() local
H A DMachineIRBuilder.cpp770 buildShuffleVector(const DstOp & Res,const SrcOp & Src1,const SrcOp & Src2,ArrayRef<int> Mask) buildShuffleVector() argument
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp70 Register Src2 = MI.getOperand(2).getReg(); in matchExtractVecEltPairwiseAdd() local
/llvm-project/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp122 Register Src0, Src1, Src2; in TEST_F() local
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/llvm-project/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp442 unsigned Src2 = UseOp->getOperandNo(); findOnlyInterestingUse() local
/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp3818 unsigned Src2 = Inst.getOperand(Inst.getNumOperands() - validateInstruction() local
3857 unsigned Src2 = Inst.getOperand(3).getReg(); validateInstruction() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1602 SDValue Src2 = Node->getOperand(2); Select() local
1661 SDValue Src2 = Node->getOperand(3); Select() local
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