Lines Matching defs:Src2

3569     MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
3582       if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
3593       MachineInstr *Def = MRI->getUniqueVRegDef(Src2->getReg());
3642     if (Src2->isReg() && Src2->getReg() == Reg) {
3700       // ChangingToImmediate adds Src2 back to the instruction.
3701       Src2->ChangeToImmediate(getImmFor(*Src2));
4011   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
4059     if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) {
4090                   .add(*Src2)
4113                   .add(*Src2)
4143             .add(*Src2)
4509   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
4511   if (Src2) {
4533         if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
4599   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
4607     if (&Use == Src2) {
4614         copyFlagsToImplicitVCC(*Inst32, *Src2);
5129     const MachineOperand &Src2 = MI.getOperand(Src2Idx);
5130     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
5132           !compareMachineOp(Src0, Src2)) {
6154     MachineOperand &Src2 = MI.getOperand(VOP3Idx[2]);
6162     if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {
6165         .add(Src2);
6166       Src2.ChangeToRegister(Reg, false);