Lines Matching defs:Src2

5247     MachineOperand &Src2 = MI.getOperand(4);
5264     if (TRI->isVectorRegister(MRI, Src2.getReg())) {
5266           .addReg(Src2.getReg());
5267       Src2.setReg(RegOp2);
5270     const TargetRegisterClass *Src2RC = MRI.getRegClass(Src2.getReg());
5277             .addReg(Src2.getReg())
5283             MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC);
5285             MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC);
5298           .addReg(Src2.getReg())
6262                                           SDValue Src2, MVT ValT) -> SDValue {
6273       Operands.push_back(Src2);
6303   SDValue Src1, Src2;
6310       Src2 = N->getOperand(3);
6329       Src2 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src2) : Src2,
6333     SDValue LaneOp = createLaneOp(Src0, Src1, Src2, MVT::i32);
6387         SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VT.getSimpleVT());
6409           Src2SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src2,
6414                 ? createLaneOp(Src0SubVec, Src1SubVec, Src2, SubVecVT)
6434     Src2 = DAG.getBitcast(VecVT, Src2);
6436   SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VecVT);
12531     // Since the mask is applied to Src1:Src2, Src1 bytes must be offset
12532     // by sizeof(Src2) = 4
13589   SDValue Src2 = N->getOperand(2);
13595     return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src2);
13609     if (isa<ConstantFPSDNode>(Src1) && !isa<ConstantFPSDNode>(Src2))
13610       std::swap(Src1, Src2);
13615     if (isClampZeroToOne(Src1, Src2))
14574     SDValue Src2 =
14583                            Src1, Src2, DAG.getTargetConstant(0, SL, MVT::i1));
15562     SDValue Src2 = Node->getOperand(5);
15566         (Src0 == Src1 || Src0 == Src2))
15586       else if (Src2.isMachineOpcode() &&
15587                Src2.getMachineOpcode() != AMDGPU::IMPLICIT_DEF)
15588         Src0 = Src2;
15600     Ops[5] = Src2;
15775       if (auto *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2)) {
15776         if (Src2->isReg() && Src2->getReg().isVirtual()) {
15777           auto *RC = TRI->getRegClassForReg(MRI, Src2->getReg());
15780             MRI.setRegClass(Src2->getReg(), NewRC);
15781             if (Src2->isTied())
16356     auto [Dst, Src0, Src1, Src2] = MI->getFirst4Regs();
16359     KB.computeKnownBitsImpl(Src2, Known2, DemandedElts, Depth + 1);