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Searched defs:ShiftVal (Results 1 – 25 of 26) sorted by relevance

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/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp289 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); getAddSubImmOpValue() local
629 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); getImm8OptLsl() local
656 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); getMoveVecShifterOpValue() local
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H A DAArch64InstPrinter.cpp1277 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); printArithExtend() local
/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp511 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1253 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); emitAddSub() local
1275 uint64_t ShiftVal = C->getZExtValue(); emitAddSub() local
1622 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); emitLogicalOp() local
1637 uint64_t ShiftVal = C->getZExtValue(); emitLogicalOp() local
4667 uint64_t ShiftVal = C->getValue().logBase2(); selectMul() local
4730 uint64_t ShiftVal = C->getZExtValue(); selectShift() local
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H A DAArch64ISelDAGToDAG.cpp675 unsigned ShiftVal = CSD->getZExtValue(); isWorthFoldingSHL() local
937 unsigned ShiftVal = 0; SelectArithExtendedRegister() local
990 unsigned ShiftVal = 0; SelectArithUXTXRegister() local
1222 unsigned ShiftVal = CSD->getZExtValue(); SelectExtendedSHL() local
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H A DAArch64InstrInfo.cpp940 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); isFalkorShiftExtFast() local
967 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); isFalkorShiftExtFast() local
975 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); isFalkorShiftExtFast() local
H A DAArch64TargetTransformInfo.cpp373 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { getIntImmCost() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp783 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
/llvm-project/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp702 unsigned ShiftVal = AArch64_AM::getArithShiftValue(OperandExtension); analyzeIndirectBranchFragment() local
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1892 __anon13ec12630802(const MachineInstr *MI, uint64_t &ShiftVal) matchShiftOfShiftedLogic() argument
2009 matchCombineMulToShl(MachineInstr & MI,unsigned & ShiftVal) matchCombineMulToShl() argument
2021 applyCombineMulToShl(MachineInstr & MI,unsigned & ShiftVal) applyCombineMulToShl() argument
2303 matchCombineShiftToUnmerge(MachineInstr & MI,unsigned TargetShiftSize,unsigned & ShiftVal) matchCombineShiftToUnmerge() argument
2327 applyCombineShiftToUnmerge(MachineInstr & MI,const unsigned & ShiftVal) applyCombineShiftToUnmerge() argument
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/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1984 uint64_t ShiftVal = C->getZExtValue(); selectShift() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2315 uint32_t ShiftVal = Shift->getZExtValue(); SelectS_BFE() local
2336 uint32_t ShiftVal = Shift->getZExtValue(); SelectS_BFE() local
H A DAMDGPUISelLowering.cpp5219 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); PerformDAGCombine() local
/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1567 SDValue ShiftVal = DAG.getNode(ISD::SRL, dl, ElementType, StVal, LowerUnalignedStoreParam() local
3371 SDValue ShiftVal = DAG.getNode(ISD::SRL, dl, ElementType, RetVal, LowerUnalignedStoreRet() local
/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp390 APInt ShiftVal = COp->getValue(); simplifyX86varShift() local
H A DX86TargetTransformInfo.cpp5642 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { getIntImmCost() local
H A DX86ISelLowering.cpp6194 uint64_t ShiftVal = N.getConstantOperandVal(1); getFauxShuffleMask() local
6794 SDValue ShiftVal = DAG.getTargetConstant(NumBits / 8, dl, MVT::i8); getVShift() local
18148 int ShiftVal = (IdxVal % 4) * 8; LowerEXTRACT_VECTOR_ELT() local
18160 int ShiftVal = (IdxVal % 2) * 8; LowerEXTRACT_VECTOR_ELT() local
30582 auto *ShiftVal = dyn_cast<ConstantInt>(I->getOperand(0)); FindSingleBitChange() local
37678 const APInt &ShiftVal = Op.getConstantOperandAPInt(1); ComputeNumSignBitsForTargetNode() local
37689 APInt ShiftVal = Op.getConstantOperandAPInt(1); ComputeNumSignBitsForTargetNode() local
48573 unsigned ShiftVal = N->getConstantOperandVal(1); combineVectorShiftImm() local
49304 unsigned ShiftVal = SplatVal.countr_one(); combineAndMaskToShift() local
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/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp409 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
H A DInstCombineCompares.cpp2277 const APInt *ShiftVal; foldICmpShlConstant() local
/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp15237 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; EmitX86BuiltinExpr() local
15278 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; EmitX86BuiltinExpr() local
15361 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; EmitX86BuiltinExpr() local
15390 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; EmitX86BuiltinExpr() local
15420 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; EmitX86BuiltinExpr() local
15441 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; EmitX86BuiltinExpr() local
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/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2399 auto ShiftVal = Op.getOperand(1); LowerShift() local
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/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7408 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); selectShiftedRegister() local
7499 uint64_t ShiftVal = 0; selectArithExtendedRegister() local
/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp1612 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); upgradeX86ALIGNIntrinsics() local
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2743 isSimpleShift(SDValue N,unsigned & ShiftVal) isSimpleShift() argument
2921 unsigned NewCCMask, ShiftVal; adjustForTestUnderMask() local
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/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5347 unsigned ShiftVal = 0; in Select() local

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