Lines Matching defs:ShiftVal

6393     uint64_t ShiftVal = N.getConstantOperandVal(1);
6395     if (NumBitsPerElt <= ShiftVal) {
6401     if ((ShiftVal % 8) != 0)
6404     uint64_t ByteShift = ShiftVal / 8;
6994   SDValue ShiftVal = DAG.getTargetConstant(NumBits / 8, dl, MVT::i8);
6995   return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
18493       int ShiftVal = (IdxVal % 4) * 8;
18494       if (ShiftVal != 0)
18496                           DAG.getConstant(ShiftVal, dl, MVT::i8));
18505       int ShiftVal = (IdxVal % 2) * 8;
18506       if (ShiftVal != 0)
18508                           DAG.getConstant(ShiftVal, dl, MVT::i8));
31396       auto *ShiftVal = dyn_cast<ConstantInt>(I->getOperand(0));
31397       if (!ShiftVal)
31399       if (ShiftVal->equalsInt(1))
38718     const APInt &ShiftVal = Op.getConstantOperandAPInt(1);
38719     if (ShiftVal.uge(VTBits))
38722     if (ShiftVal.uge(Tmp))
38724     return Tmp - ShiftVal.getZExtValue();
38729     APInt ShiftVal = Op.getConstantOperandAPInt(1);
38730     if (ShiftVal.uge(VTBits - 1))
38733     ShiftVal += Tmp;
38734     return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue();
49923   unsigned ShiftVal = N->getConstantOperandVal(1);
49924   if (ShiftVal >= NumBitsPerElt) {
49927     ShiftVal = NumBitsPerElt - 1;
49931   if (!ShiftVal)
49961     return MergeShifts(N0.getOperand(0), ShiftVal, N0.getConstantOperandVal(1));
49966     return MergeShifts(N0.getOperand(0), ShiftVal, 1);
49969   if (LogicalShift && (ShiftVal % 8) == 0) {
49979   if (Opcode == X86ISD::VSRAI && NumBitsPerElt == 32 && ShiftVal == 31 &&
50015         Elt <<= ShiftVal;
50017         Elt.ashrInPlace(ShiftVal);
50019         Elt.lshrInPlace(ShiftVal);
50641   unsigned ShiftVal = SplatVal.countr_one();
50642   SDValue ShAmt = DAG.getTargetConstant(EltBitWidth - ShiftVal, DL, MVT::i8);