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Searched defs:SOffset (Results 1 – 12 of 12) sorted by relevance

/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1339 SelectMUBUF(SDValue Addr,SDValue & Ptr,SDValue & VAddr,SDValue & SOffset,SDValue & Offset,SDValue & Offen,SDValue & Idxen,SDValue & Addr64) const SelectMUBUF() argument
1427 SelectMUBUFAddr64(SDValue Addr,SDValue & SRsrc,SDValue & VAddr,SDValue & SOffset,SDValue & Offset) const SelectMUBUFAddr64() argument
1469 SelectMUBUFScratchOffen(SDNode * Parent,SDValue Addr,SDValue & Rsrc,SDValue & VAddr,SDValue & SOffset,SDValue & ImmOffset) const SelectMUBUFScratchOffen() argument
1547 SelectMUBUFScratchOffset(SDNode * Parent,SDValue Addr,SDValue & SRsrc,SDValue & SOffset,SDValue & Offset) const SelectMUBUFScratchOffset() argument
1589 SelectMUBUFOffset(SDValue Addr,SDValue & SRsrc,SDValue & SOffset,SDValue & Offset) const SelectMUBUFOffset() argument
2010 isSOffsetLegalWithImmOffset(SDValue * SOffset,bool Imm32Only,bool IsBuffer,int64_t ImmOffset) const isSOffsetLegalWithImmOffset() argument
2028 SelectSMRDOffset(SDValue ByteOffsetNode,SDValue * SOffset,SDValue * Offset,bool Imm32Only,bool IsBuffer,bool HasSOffset,int64_t ImmOffset) const SelectSMRDOffset() argument
2120 SelectSMRDBaseOffset(SDValue Addr,SDValue & SBase,SDValue * SOffset,SDValue * Offset,bool Imm32Only,bool IsBuffer,bool HasSOffset,int64_t ImmOffset) const SelectSMRDBaseOffset() argument
2170 SelectSMRD(SDValue Addr,SDValue & SBase,SDValue * SOffset,SDValue * Offset,bool Imm32Only) const SelectSMRD() argument
2204 SelectSMRDSgprImm(SDValue Addr,SDValue & SBase,SDValue & SOffset,SDValue & Offset) const SelectSMRDSgprImm() argument
2221 SelectSMRDBufferSgprImm(SDValue N,SDValue & SOffset,SDValue & Offset) const SelectSMRDBufferSgprImm() argument
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H A DAMDGPUInstructionSelector.cpp4180 selectSmrdOffset(MachineOperand & Root,Register & Base,Register * SOffset,int64_t * Offset) const selectSmrdOffset() argument
4293 Register Base, SOffset; selectSmrdSgpr() local
4303 Register Base, SOffset; selectSmrdSgprImm() local
5122 splitIllegalMUBUFOffset(MachineIRBuilder & B,Register & SOffset,int64_t & ImmOffset) const splitIllegalMUBUFOffset() argument
5136 selectMUBUFAddr64Impl(MachineOperand & Root,Register & VAddr,Register & RSrcReg,Register & SOffset,int64_t & Offset) const selectMUBUFAddr64Impl() argument
5186 selectMUBUFOffsetImpl(MachineOperand & Root,Register & RSrcReg,Register & SOffset,int64_t & Offset) const selectMUBUFOffsetImpl() argument
5214 Register SOffset; selectMUBUFAddr64() local
5249 Register SOffset; selectMUBUFOffset() local
5277 Register SOffset = Root.getReg(); selectBUFSOffset() local
5329 Register SOffset; selectSMRDBufferSgprImm() local
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H A DSIRegisterInfo.cpp915 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); resolveFrameIndex() local
1347 MCRegister SOffset = ScratchOffsetReg; buildSpillLoadStore() local
2569 auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset); eliminateFrameIndex() local
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H A DSIISelLowering.cpp8775 selectSOffset(SDValue SOffset,SelectionDAG & DAG,const GCNSubtarget * Subtarget) selectSOffset() argument
8790 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); lowerRawBufferAtomicIntrin() local
8818 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); lowerStructBufferAtomicIntrin() local
8908 auto SOffset = selectSOffset(Op.getOperand(4), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8933 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8953 auto SOffset = selectSOffset(Op.getOperand(4), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
8980 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
9107 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
9130 auto SOffset = selectSOffset(Op.getOperand(7), DAG, Subtarget); LowerINTRINSIC_W_CHAIN() local
9553 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); LowerINTRINSIC_VOID() local
9581 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_VOID() local
9626 auto SOffset = selectSOffset(Op.getOperand(5), DAG, Subtarget); LowerINTRINSIC_VOID() local
9677 auto SOffset = selectSOffset(Op.getOperand(6), DAG, Subtarget); LowerINTRINSIC_VOID() local
10016 uint32_t SOffset, ImmOffset; setBufferOffsets() local
10027 uint32_t SOffset, ImmOffset; setBufferOffsets() local
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H A DAMDGPURegisterBankInfo.cpp1273 return SOffset + ImmOffset; in setBufferOffsets() local
1255 uint32_t SOffset, ImmOffset; setBufferOffsets() local
1363 Register SOffset; applyMappingSBufferLoad() local
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H A DAMDGPULegalizerInfo.cpp5839 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); legalizeBufferStore() local
5892 buildBufferLoad(unsigned Opc,Register LoadDstReg,Register RSrc,Register VIndex,Register VOffset,Register SOffset,unsigned ImmOffset,unsigned Format,unsigned AuxiliaryData,MachineMemOperand * MMO,bool IsTyped,bool HasVIndex,MachineIRBuilder & B) buildBufferLoad() argument
5950 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); legalizeBufferLoad() local
6185 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); legalizeBufferAtomic() local
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H A DSILoadStoreOptimizer.cpp97 bool SOffset = false; global() member
H A DSIInstrInfo.cpp444 if (SOffset->isReg()) in getMemOperandsWithOffsetWidth() local
6854 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); legalizeOperands() local
9040 splitMUBUFOffset(uint32_t Imm,uint32_t & SOffset,uint32_t & ImmOffset,Align Alignment) const splitMUBUFOffset() argument
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H A DGCNHazardRecognizer.cpp831 const MachineOperand *SOffset = createsVALUHazard() local
/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp722 unsigned SOffset = 0; getMachineOpValue() local
/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp332 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp5656 isAArch64FrameOffsetLegal(const MachineInstr & MI,StackOffset & SOffset,bool * OutUseUnscaledOp,unsigned * OutUnscaledOp,int64_t * EmittableOffset) isAArch64FrameOffsetLegal() argument