Lines Matching defs:SOffset

4633                                                  Register *SOffset,
4649   if (SOffset && Offset) {
4659           *SOffset = OffsetReg;
4665           // to be negative if the resulting (Offset + (M0 or SOffset or zero)
4666           // is negative. Handle the case where the Immediate Offset + SOffset
4668           auto SKnown = KB->getKnownBits(*SOffset);
4688   if (SOffset && GEPI.SgprParts.size() == 1 && isUInt<32>(GEPI.Imm) &&
4695     *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
4696     BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), *SOffset)
4701   if (SOffset && GEPI.SgprParts.size() && GEPI.Imm == 0) {
4704       *SOffset = OffsetReg;
4716   if (!selectSmrdOffset(Root, Base, /* SOffset= */ nullptr, &Offset))
4746   Register Base, SOffset;
4747   if (!selectSmrdOffset(Root, Base, &SOffset, /* Offset= */ nullptr))
4751            [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};
4756   Register Base, SOffset;
4758   if (!selectSmrdOffset(Root, Base, &SOffset, &Offset))
4762            [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },
5565 /// immediate field. Modifies \p ImmOffset and sets \p SOffset to the variable
5568   MachineIRBuilder &B, Register &SOffset, int64_t &ImmOffset) const {
5573   SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
5575     .addDef(SOffset)
5582   Register &SOffset, int64_t &Offset) const {
5627   splitIllegalMUBUFOffset(B, SOffset, Offset);
5632   MachineOperand &Root, Register &RSrcReg, Register &SOffset,
5652   splitIllegalMUBUFOffset(B, SOffset, Offset);
5660   Register SOffset;
5663   if (!selectMUBUFAddr64Impl(Root, VAddr, RSrcReg, SOffset, Offset))
5676         if (SOffset)
5677           MIB.addReg(SOffset);
5695   Register SOffset;
5698   if (!selectMUBUFOffsetImpl(Root, RSrcReg, SOffset, Offset))
5706         if (SOffset)
5707           MIB.addReg(SOffset);
5723   Register SOffset = Root.getReg();
5725   if (STI.hasRestrictedSOffset() && mi_match(SOffset, *MRI, m_ZeroInt()))
5726     SOffset = AMDGPU::SGPR_NULL;
5728   return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};
5776   Register SOffset;
5778   std::tie(SOffset, Offset) = AMDGPU::getBaseWithConstantOffset(
5780   if (!SOffset)
5788   assert(MRI->getType(SOffset) == LLT::scalar(32));
5789   return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },