| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 34 SHL = 0x17, enumerator
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 165 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, addIPMSequence() local
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| H A D | SystemZISelLowering.cpp | 7643 auto *SHL = CompareLHS->getOperand(0).getNode(); combineCCMask() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 165 SHL, global() enumerator
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 719 SHL, global() enumerator
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4153 SDValue SHL = LowerINTRINSIC_WO_CHAIN() local
13989 SDValue SHL = N->getOperand(0); PerformSHLSimplify() local
14369 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), CombineANDShift() local
14380 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), CombineANDShift() local
14393 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), CombineANDShift() local
14406 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), CombineANDShift() local
14486 SDValue SHL = OR->getOperand(1); PerformORCombineToSMULWBT() local
17767 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), PerformShiftCombine() local
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 2279 WeightedLeaf SHL = Leaves.findSHL(31); balanceSubTree() local
[all...] |
| /llvm-project/llvm/include/llvm/TableGen/ |
| H A D | Record.h | 907 SHL, global() enumerator
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 11345 SDValue SHL = DAG.getNode(X86ISD::VSHLI, DL, RotateVT, V1, lowerShuffleAsBitRotate() local
29325 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT, R, LowerShiftByScalarImmediate() local
30424 SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt); LowerRotate() local
[all...] |