Lines Matching defs:SHL
1326 setOperationAction(ISD::SHL, VT, Custom);
1534 setOperationAction(ISD::SHL, VT, Custom);
1971 setOperationAction(ISD::SHL, VT, Custom);
2652 ISD::SHL,
3517 return NewShiftOpcode == ISD::SHL;
3543 if (ShiftOpc == ISD::SHL || ShiftOpc == ISD::SRL) {
3556 if (ShiftOpc == ISD::SHL) {
3572 return AndMask->getSignificantBits() > 33 ? (unsigned)ISD::SHL : ShiftOpc;
3575 return ShiftOrRotateAmt.ult(7) ? (unsigned)ISD::SHL : ShiftOpc;
3611 assert(((N->getOpcode() == ISD::SHL &&
3614 N->getOperand(0).getOpcode() == ISD::SHL)) &&
6367 case ISD::SHL:
6380 if (ISD::SHL == Opcode) {
6787 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt,
6816 NextElt = DAG.getNode(ISD::SHL, DL, MVT::i32, NextElt,
8600 case ISD::SHL:
11575 // expanded to OR(SRL,SHL), will be more efficient, but if they can
11584 SDValue SHL = DAG.getNode(X86ISD::VSHLI, DL, RotateVT, V1,
11588 SDValue Rot = DAG.getNode(ISD::OR, DL, RotateVT, SHL, SRL);
17892 case ISD::SHL:
19343 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
20482 Adjust = DAG.getNode(ISD::SHL, DL, MVT::i64, Zext, Const63);
21015 In = DAG.getNode(ISD::SHL, DL, ExtVT,
21068 In = DAG.getNode(ISD::SHL, DL, InVT, In,
23000 case ISD::SHL:
23365 if (Op1.getOpcode() == ISD::SHL)
23367 if (Op0.getOpcode() == ISD::SHL) {
23866 // ICMP_EQ(AND(X,C),C) -> SRA(SHL(X,LOG2(C)),BW-1) iff C is power-of-2.
23875 Result = DAG.getNode(ISD::SHL, dl, VT, Result,
24507 case ISD::SHL:
24541 // SELECT (AND(X,1) == 0), Y, (SHL Y, Z) -> (SHL Y, (AND NEG(AND(X,1)), Z))
25653 case ISD::SHL:
25703 ShiftOpc = ISD::SHL;
27192 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
27626 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
28335 DAG.getNode(ISD::SHL, DL, MVT::i32, NewRM,
28339 DAG.getNode(ISD::SHL, DL, MVT::i16, DAG.getConstant(0xc9, DL, MVT::i16),
28373 RMBits = DAG.getNode(ISD::SHL, DL, MVT::i32, RMBits,
28512 case ISD::SHL:
28522 return getGFNICtrlImm(ISD::SRL, 8 - Amt) | getGFNICtrlImm(ISD::SHL, Amt);
28524 return getGFNICtrlImm(ISD::SHL, 8 - Amt) | getGFNICtrlImm(ISD::SRL, Amt);
29349 LoOp = DAG.getNode(ISD::SHL, dl, MVT::i16, LoOp,
29351 HiOp = DAG.getNode(ISD::SHL, dl, MVT::i16, HiOp,
29762 assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
29798 assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
29886 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1) {
29907 if ((Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL) &&
29920 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1) {
29951 if (Op.getOpcode() == ISD::SHL) {
29953 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT, R,
29955 SHL = DAG.getBitcast(VT, SHL);
29958 return DAG.getNode(ISD::AND, dl, VT, SHL, DAG.getConstant(Mask, dl, VT));
30007 unsigned LogicalOp = (Opcode == ISD::SHL ? ISD::SHL : ISD::SRL);
30015 if (Opcode != ISD::SHL)
30081 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
30149 if (Opc == ISD::SHL || Opc == ISD::SRL)
30211 (VT == MVT::v4i32 || Subtarget.hasSSE41() || Opc != ISD::SHL ||
30221 // Constant ISD::SRA/SRL/SHL can be performed efficiently on vXiN vectors by
30380 if (Opc == ISD::SHL && !(VT == MVT::v32i8 && (Subtarget.hasXOP() ||
30493 if (Opc == ISD::SHL)
30543 Amt = DAG.getNode(ISD::SHL, dl, ExVT, DAG.getConstant(1, dl, ExVT), Amt);
30618 if (Opc == ISD::SHL || Opc == ISD::SRL) {
30829 supportedVectorShiftWithImm(WideVT, Subtarget, ISD::SHL)))) {
30836 DAG.getNode(ISD::SHL, DL, WideVT, DAG.getBitcast(WideVT, Op0),
30848 SDValue ShX = DAG.getNode(ISD::SHL, DL, VT, Op0,
30863 unsigned ShiftOpc = IsFSHR ? ISD::SRL : ISD::SHL;
30955 SDValue Res = DAG.getNode(ISD::SHL, DL, MVT::i32, Op0, HiShift);
30960 Res = DAG.getNode(ISD::SHL, DL, MVT::i32, Res, Amt);
31075 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, R,
31121 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL;
31191 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL;
31192 unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL;
31198 Amt = DAG.getNode(ISD::SHL, DL, ExtVT, Amt, DAG.getConstant(5, DL, ExtVT));
31231 bool LegalVarShifts = supportedVectorVarShift(VT, Subtarget, ISD::SHL) &&
31240 SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt);
31241 SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR);
31242 return DAG.getNode(ISD::OR, DL, VT, SHL, SRL);
31954 Hi = DAG.getNode(ISD::SHL, DL, MVT::i64, Hi,
31963 Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
32097 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), ShifterV);
32231 Op = DAG.getNode(ISD::SHL, DL, MVT::i32, Op,
33314 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
45022 case ISD::SHL: {
45023 // If we find a suitable source, a SHL becomes a KSHIFTL.
46522 SDValue Mask = DAG.getNode(ISD::SHL, dl, BCVT, MaskBit, MaskIdx);
47456 // Unlike general shift instructions (SHL/SRL), AVX2's VSHLV/VSRLV handle
47465 if ((LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SHL) &&
47477 if ((RHS.getOpcode() == ISD::SRL || RHS.getOpcode() == ISD::SHL) &&
47607 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And.getOperand(0), ShlAmt);
47780 // If Src came from a SHL (probably from an expanded SIGN_EXTEND_INREG), then
47782 if (Src.getOpcode() == ISD::SHL) {
48513 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
48849 Result = DAG.getNode(ISD::SHL, DL, VT, Result,
48918 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
48920 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
49119 // implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.
49172 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
49179 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
49197 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
49204 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
49215 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
49224 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
49244 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
49247 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
49326 supportedVectorVarShift(VT, Subtarget, ISD::SHL)) {
49401 // fold (SRA (SHL X, ShlConst), SraConst)
49402 // into (SHL (sext_in_reg X), ShlConst - SraConst)
49416 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
49441 return DAG.getNode(ISD::SHL, DL, VT, NN,
50658 if (ShiftedIndex.getOpcode() != ISD::SHL)
51142 SDValue Shift = DAG.getNode(ISD::SHL, dl, VT, Neg,
55063 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
56480 if ((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) &&
57789 // Special case: SHL/SRL AVX1 V4i64 by 32-bits can lower as a shuffle.
58737 case ISD::SHL:
58754 if (supportedVectorShiftWithImm(VT, Subtarget, ISD::SHL) &&
59027 Src = DAG.getNode(ISD::SHL, dl, NVT, Src, DAG.getConstant(16, dl, NVT));
59368 case ISD::SHL: return combineShiftLeft(N, DAG, Subtarget);
59551 if (Opc == ISD::SHL && VT.isVector() && VT.getVectorElementType() == MVT::i8)
59562 if ((Opc == ISD::MUL || Opc == ISD::SHL) && VT == MVT::i8)
59577 case ISD::SHL:
59692 case ISD::SHL: