Lines Matching defs:SHL
205 setOperationAction(ISD::SHL, VT, Custom);
268 setOperationAction(ISD::SHL, VT, Custom);
1015 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT,
1197 setOperationAction(ISD::SHL, MVT::i64, Custom);
1617 setTargetDAGCombine(ISD::SHL);
2032 if (Op.getOpcode() != ISD::SHL)
3751 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
4230 SDValue SHL =
4231 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
4233 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
4249 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4918 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4930 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
6389 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
6428 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
6433 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
6441 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6493 RMValue = DAG.getNode(ISD::SHL, DL, MVT::i32, RMValue,
6722 if (N->getOpcode() == ISD::SHL) {
6755 // We can get here for a node like i32 = ISD::SHL i32, i64
6760 N->getOpcode() == ISD::SHL) &&
6804 if (!isOneConstant(N->getOperand(1)) || N->getOpcode() == ISD::SHL)
10648 case ISD::SHL:
10788 case ISD::SHL:
13850 assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
13865 if (N->getOpcode() != ISD::SHL)
13872 if (N->getOpcode() != ISD::SHL)
13898 (N->getOperand(0).getOpcode() == ISD::SHL ||
13910 if (N->getOperand(0).getOpcode() == ISD::SHL)
13921 assert(((N->getOpcode() == ISD::SHL &&
13924 N->getOperand(0).getOpcode() == ISD::SHL)) &&
14016 if (U->getOperand(0).getOpcode() == ISD::SHL ||
14017 U->getOperand(1).getOpcode() == ISD::SHL)
14027 if (N->getOperand(0).getOpcode() != ISD::SHL)
14030 SDValue SHL = N->getOperand(0);
14033 auto *C2 = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
14063 SDValue X = SHL.getOperand(0);
14067 SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1));
14069 LLVM_DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump();
14070 SHL.dump(); N->dump());
14309 DAG.getNode(ISD::SHL, DL, VT,
14316 DAG.getNode(ISD::SHL, DL, VT,
14329 DAG.getNode(ISD::SHL, DL, VT,
14337 DAG.getNode(ISD::SHL, DL, VT,
14348 Res = DAG.getNode(ISD::SHL, DL, VT,
14379 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
14382 bool LeftShift = N0->getOpcode() == ISD::SHL;
14410 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
14412 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
14421 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14423 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL,
14434 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
14436 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL,
14447 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
14449 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL,
14461 return DAG.getNode(ISD::SHL, DL, MVT::i32, And,
14527 SDValue SHL = OR->getOperand(1);
14529 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
14531 SHL = OR->getOperand(0);
14533 if (!isSRL16(SRL) || !isSHL16(SHL))
14538 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) ||
14544 SHL.getOperand(0) != SDValue(SMULLOHI, 1))
14682 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
17781 if (ST->isThumb1Only() && N->getOpcode() == ISD::SHL && VT == MVT::i32 &&
17806 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
17809 ISD::SRL, DL, MVT::i32, SHL,
17827 case ISD::SHL:
18570 // Result = if K != 0 then (SHL t2:0, K) else t2:0
18577 // Result = if K != 0 then (SHL t2:0, K) else t2:0
18593 Res = DAG.getNode(ISD::SHL, dl, VT, Res,
18972 case ISD::SHL:
19352 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM))
20206 ISD::SHL, SDLoc(Op), MVT::i32, Op.getOperand(1),