| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelLowering.cpp | 409 getOpndList(SmallVectorImpl<SDValue> &Ops, in getOpndList()
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| H A D | MipsISelLowering.cpp | 3074 getOpndList(SmallVectorImpl<SDValue> & Ops,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,bool IsPICCall,bool GlobalOrExternal,bool InternalLinkage,bool IsCallReloc,CallLoweringInfo & CLI,SDValue Callee,SDValue Chain) const getOpndList() argument
3295 std::deque<std::pair<unsigned, SDValue>> RegsToPass; LowerCall() local
4429 passByValArg(SDValue Chain,const SDLoc & DL,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,SmallVectorImpl<SDValue> & MemOpChains,SDValue StackPtr,MachineFrameInfo & MFI,SelectionDAG & DAG,SDValue Arg,unsigned FirstReg,unsigned LastReg,const ISD::ArgFlagsTy & Flags,bool isLittle,const CCValAssign & VA) const passByValArg() argument
[all...] |
| H A D | MipsSEISelLowering.cpp | 1163 getOpndList(SmallVectorImpl<SDValue> & Ops,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,bool IsPICCall,bool GlobalOrExternal,bool InternalLinkage,bool IsCallReloc,CallLoweringInfo & CLI,SDValue Callee,SDValue Chain) const getOpndList() argument
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| /llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 324 std::deque<std::pair<unsigned, SDValue>> RegsToPass; LowerCall() local
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| /llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 296 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; in LowerCall() local
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| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 451 SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass; LowerCall() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 714 Passv64i1ArgInRegs(const SDLoc & DL,SelectionDAG & DAG,SDValue & Arg,SmallVectorImpl<std::pair<Register,SDValue>> & RegsToPass,CCValAssign & VA,CCValAssign & NextVA,const X86Subtarget & Subtarget) Passv64i1ArgInRegs() argument
2141 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass; LowerCall() local
[all...] |
| /llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 823 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; LowerCCCCallTo() local
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| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 568 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass; LowerCall() local
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| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 659 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; LowerCCCCallTo() local
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| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 887 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; in LowerCall_32() local
1266 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass; LowerCall_64() local
[all...] |
| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1535 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; LowerCall() local
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| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1046 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; LowerCCCCallTo() local
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| /llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 631 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; LowerCall() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 5713 buildCallOperands(SmallVectorImpl<SDValue> & Ops,PPCTargetLowering::CallFlags CFlags,const SDLoc & dl,SelectionDAG & DAG,SmallVector<std::pair<unsigned,SDValue>,8> & RegsToPass,SDValue Glue,SDValue Chain,SDValue & Callee,int SPDiff,const PPCSubtarget & Subtarget) buildCallOperands() argument
5794 FinishCall(CallFlags CFlags,const SDLoc & dl,SelectionDAG & DAG,SmallVector<std::pair<unsigned,SDValue>,8> & RegsToPass,SDValue Glue,SDValue Chain,SDValue CallSeqStart,SDValue & Callee,int SPDiff,unsigned NumBytes,const SmallVectorImpl<ISD::InputArg> & Ins,SmallVectorImpl<SDValue> & InVals,const CallBase * CB) const FinishCall() argument
6090 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; LowerCall_32SVR4() local
6424 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; LowerCall_64SVR4() local
7546 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; LowerCall_AIX() local
[all...] |
| /llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 631 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; in LowerCall() local
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| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4245 SmallVector<std::pair<Register, SDValue>> RegsToPass; LowerCall() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 457 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; LowerCall() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 3301 passSpecialInputs(CallLoweringInfo & CLI,CCState & CCInfo,const SIMachineFunctionInfo & Info,SmallVectorImpl<std::pair<unsigned,SDValue>> & RegsToPass,SmallVectorImpl<SDValue> & MemOpChains,SDValue Chain) const passSpecialInputs() argument
3686 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; LowerCall() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1935 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass; LowerCall() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 2343 PassF64ArgInRegs(const SDLoc & dl,SelectionDAG & DAG,SDValue Chain,SDValue & Arg,RegsToPassVector & RegsToPass,CCValAssign & VA,CCValAssign & NextVA,SDValue & StackPtr,SmallVectorImpl<SDValue> & MemOpChains,bool IsTailCall,int SPDiff) const PassF64ArgInRegs() argument
2504 RegsToPassVector RegsToPass; LowerCall() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 19898 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass; LowerCall() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 8361 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; LowerCall() local
[all...] |