| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 132 getFrameHelperName(SmallVectorImpl<unsigned> & Regs,FrameHelperType Type,unsigned FpOffset) getFrameHelperName() argument
314 getOrCreateFrameHelper(Module * M,MachineModuleInfo * MMI,SmallVectorImpl<unsigned> & Regs,FrameHelperType Type,unsigned FpOffset=0) getOrCreateFrameHelper() argument
397 shouldUseFrameHelper(MachineBasicBlock & MBB,MachineBasicBlock::iterator & NextMBBI,SmallVectorImpl<unsigned> & Regs,FrameHelperType Type) shouldUseFrameHelper() argument
475 SmallVector<unsigned, 8> Regs; lowerEpilog() local
558 SmallVector<unsigned, 8> Regs; lowerProlog() local
[all...] |
| H A D | AArch64ISelDAGToDAG.cpp | 1394 createDTuple(ArrayRef<SDValue> Regs) createDTuple() argument
1403 createQTuple(ArrayRef<SDValue> Regs) createQTuple() argument
1412 createZTuple(ArrayRef<SDValue> Regs) createZTuple() argument
1422 createZMulTuple(ArrayRef<SDValue> Regs) createZMulTuple() argument
1434 createTuple(ArrayRef<SDValue> Regs,const unsigned RegClassIDs[],const unsigned SubRegs[]) createTuple() argument
1472 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, SelectTable() local
1771 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectCVTIntrinsic() local
1795 SmallVector<SDValue, 4> Regs(N->op_begin() + StartIdx, SelectDestructiveMultiIntrinsic() local
1930 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectClamp() local
2057 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, SelectUnaryMultiIntrinsic() local
2082 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); SelectStore() local
2101 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); SelectPredicatedStore() local
2146 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectPostStore() local
2200 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); SelectLoadLane() local
2238 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectPostLoadLane() local
2292 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); SelectStoreLane() local
2320 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); SelectPostStoreLane() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 243 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
253 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
262 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); getReservedRegs() local
435 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); getFrameRegister() local
[all...] |
| H A D | SystemZFrameLowering.cpp | 924 auto *Regs = isXPLeafCandidate() local
973 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); assignCalleeSavedSpillSlots() local
1076 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); determineCalleeSaves() local
1094 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); spillCalleeSavedRegisters() local
1156 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); restoreCalleeSavedRegisters() local
1213 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); emitPrologue() local
1328 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); emitEpilogue() local
1462 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); processFunctionBeforeFrameFinalized() local
1507 auto *Regs = determineFrameLayout() local
[all...] |
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
349 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
363 ArrayRef<MCPhysReg> AllocateRegBlock(ArrayRef<MCPhysReg> Regs, in AllocateRegBlock() argument
390 AllocateReg(ArrayRef<MCPhysReg> Regs,const MCPhysReg * ShadowRegs) AllocateReg() argument
[all...] |
| H A D | RegisterPressure.h | 276 RegSet Regs; variable
|
| /llvm-project/llvm/include/llvm/MCA/ |
| H A D | HWEventListener.h | 78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
|
| /llvm-project/bolt/include/bolt/Passes/ |
| H A D | ReachingDefOrUse.h | 131 BitVector Regs = BitVector(this->BC.MRI->getNumRegs(), false); in computeNext() local
|
| /llvm-project/llvm/tools/llvm-exegesis/lib/ |
| H A D | RegisterAliasing.cpp | 82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString() argument
|
| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 145 static const unsigned Regs[2][2] = { getFrameRegister() local
|
| /llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 381 for (auto &RE : Regs) { in EmitRegMappingTables() argument
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); EmitRegUnitPressure() local
508 EmitRegMapping(raw_ostream & OS,const std::deque<CodeGenRegister> & Regs,bool isCtor) EmitRegMapping() argument
872 const auto &Regs = RegBank.getRegisters(); runMCDesc() local
1440 const auto &Regs = RegBank.getRegisters(); runTargetDesc() local
1676 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); runTargetDesc() local
[all...] |
| /llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | Taint.cpp | 139 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); addPartialTaint() local
283 if (const TaintedSubRegions *Regs = getTaintedSymbolsImpl() local
|
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 99 __anon7932dd590202(RegList &Regs, RegisterSet &UsesDefs) INITIALIZE_PASS() argument
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 801 AddressRegs Regs = getRegs(Opc, *LSO.TII); setMI() local
1492 AddressRegs Regs = getRegs(Opcode, *TII); mergeBufferLoadPair() local
1533 AddressRegs Regs = getRegs(Opcode, *TII); mergeTBufferLoadPair() local
1576 AddressRegs Regs = getRegs(Opcode, *TII); mergeTBufferStorePair() local
1863 AddressRegs Regs = getRegs(Opcode, *TII); mergeBufferStorePair() local
[all...] |
| H A D | AMDGPUArgumentUsageInfo.h | 97 SmallVector<MCRegister> Regs; global() member
|
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 80 std::vector<unsigned> &Regs, in GetGroupRegs() argument
546 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters() local
[all...] |
| H A D | ExecutionDomainFix.cpp | 329 SmallVector<int, 4> Regs; in visitSoftInstr() local
|
| H A D | CallingConvLower.cpp | 201 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType() argument
|
| H A D | RDFRegisters.cpp | 367 BitVector Regs = PRI.getUnitAliases(U); in makeRegRef() local
|
| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | IRTranslator.h | 708 assert(Regs.size() == 1 && in getOrCreateVReg() local
718 auto &Regs = *VMap.getVRegs(Token); getOrCreateConvergenceTokenVReg() local
|
| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 215 RegUnitIterator(const CodeGenRegister::Vec &Regs) in RegUnitIterator() argument
1200 std::vector<Record *> Regs = Records.getAllDerivedDefinitions("Register"); CodeGenRegBank() local
1711 CodeGenRegister::Vec Regs; global() member
1740 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); computeUberSets() local
2510 computeCoveredRegisters(ArrayRef<Record * > Regs) computeCoveredRegisters() argument
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUPALMetadata.cpp | 171 auto Regs = getRegisters(); in getRegister() local
772 auto Regs = getRegisters(); toString() local
|
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 35 SmallVector<Register, 1> Regs; member in __anon7be7f31b0111::GISelAsmOperandInfo
|
| /llvm-project/bolt/lib/Passes/ |
| H A D | TailDuplication.cpp | 83 void TailDuplication::getCallerSavedRegs(const MCInst &Inst, BitVector &Regs, in getCallerSavedRegs()
|
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 239 createTuple(SelectionDAG & CurDAG,ArrayRef<SDValue> Regs,unsigned NF,RISCVII::VLMUL LMUL) createTuple() argument
350 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, selectVLSEG() local
390 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, selectVLSEGFF() local
432 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, selectVLXSEG() local
483 SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); selectVSSEG() local
513 SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); selectVSXSEG() local
|